[clang] [llvm] [RISCV] Add support for Ziccid 1.0 (PR #196459)
Liao Chunyu via cfe-commits
cfe-commits at lists.llvm.org
Thu May 7 19:11:28 PDT 2026
https://github.com/ChunyuLiao created https://github.com/llvm/llvm-project/pull/196459
No codegen and instruction.
It may be ratified in the future.
We can wait until the extension is ratified before revisiting this patch https://github.com/riscv/riscv-isa-manual/pull/2598
>From 693cc2e6bf783a96a4da05f8fa6727489e79596d Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 7 May 2026 21:22:00 -0400
Subject: [PATCH] ziccid
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 +
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++
llvm/test/CodeGen/RISCV/attributes.ll | 2 ++
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
8 files changed, 22 insertions(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 83920246d5dad..d0a773f8f43d8 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -21,6 +21,7 @@
// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
// CHECK-NEXT: ziccamoc 1.0 'Ziccamoc' (Main Memory Supports Atomics in Zacas)
+// CHECK-NEXT: ziccid 1.0 'Ziccid' (Instruction/Data Coherence and Consistency)
// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 3882f2889eb59..6682948869f94 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -116,6 +116,7 @@
// CHECK-NOT: __riscv_zicboz {{.*$}}
// CHECK-NOT: __riscv_ziccamoa {{.*$}}
// CHECK-NOT: __riscv_ziccamoc {{.*$}}
+// CHECK-NOT: __riscv_ziccid {{.*$}}
// CHECK-NOT: __riscv_ziccif {{.*$}}
// CHECK-NOT: __riscv_zicclsm {{.*$}}
// CHECK-NOT: __riscv_ziccrse {{.*$}}
@@ -897,6 +898,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s
// CHECK-ZICCAMOC-EXT: __riscv_ziccamoc 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iziccid -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCID-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iziccid -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCID-EXT %s
+// CHECK-ZICCID-EXT: __riscv_ziccid 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32iziccif -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2c8805f5fe796..2b68827e7b136 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -206,6 +206,7 @@ on support follow.
``Zicboz`` Assembly Support
``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Ziccamoc`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Ziccid`` Supported
``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b905870a482ff..a92fb63e3c3cd 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -116,6 +116,10 @@ def FeatureStdExtZiccif
: RISCVExtension<1, 0,
"Main Memory Supports Instruction Fetch with Atomicity Requirement">;
+def FeatureStdExtZiccid
+ : RISCVExtension<1, 0,
+ "Instruction/Data Coherence and Consistency", [FeatureStdExtZiccif]>;
+
def FeatureStdExtZicclsm
: RISCVExtension<1, 0, "Main Memory Supports Misaligned Loads/Stores">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9da6766692e99..2c1ae20ee44c1 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -242,6 +242,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOC %s
+; RUN: llc -mtriple=riscv64 -mattr=+ziccid %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCID %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccif %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCIF %s
; RUN: llc -mtriple=riscv64 -mattr=+zicclsm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCLSM %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccrse %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCRSE %s
@@ -563,6 +564,7 @@
; RV64ZCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0"
; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
; RV64ZICCAMOC: .attribute 5, "rv64i2p1_ziccamoc1p0"
+; RV64ZICCID: .attribute 5, "rv64i2p1_ziccid1p0_ziccif1p0"
; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0"
; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0"
; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 92e033cb90dc9..d4b920c08a096 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -305,6 +305,7 @@
; CHECK-NEXT: zicboz - 'Zicboz' (Cache-Block Zero Instructions).
; CHECK-NEXT: ziccamoa - 'Ziccamoa' (Main Memory Supports All Atomics in A).
; CHECK-NEXT: ziccamoc - 'Ziccamoc' (Main Memory Supports Atomics in Zacas).
+; CHECK-NEXT: ziccid - 'Ziccid' (Instruction/Data Coherence and Consistency).
; CHECK-NEXT: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).
; CHECK-NEXT: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).
; CHECK-NEXT: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 241fac8f2bd17..ef5e091e7e41e 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -109,6 +109,9 @@
.attribute arch, "rv32iziccamoc"
# CHECK: attribute 5, "rv32i2p1_ziccamoc1p0"
+.attribute arch, "rv32iziccid"
+# CHECK: attribute 5, "rv32i2p1_ziccid1p0_ziccif1p0"
+
.attribute arch, "rv32iziccif"
# CHECK: attribute 5, "rv32i2p1_ziccif1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index e96e2d9d462dc..d28066d423b77 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1152,6 +1152,7 @@ R"(All available -march extensions for RISC-V
zicboz 1.0
ziccamoa 1.0
ziccamoc 1.0
+ ziccid 1.0
ziccif 1.0
zicclsm 1.0
ziccrse 1.0
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