[clang] cc35d56 - [CIR][RISCV] Support zksed builtin codegen (#196250)

[via cfe-commits]

Author: Jianjian Guan
Date: 2026-05-08T10:06:39+08:00
New Revision: cc35d56bb8e9ce2caf4b7f397d7377b88464df9d

URL: https://github.com/llvm/llvm-project/commit/cc35d56bb8e9ce2caf4b7f397d7377b88464df9d
DIFF: https://github.com/llvm/llvm-project/commit/cc35d56bb8e9ce2caf4b7f397d7377b88464df9d.diff

LOG: [CIR][RISCV] Support zksed builtin codegen (#196250)

Added: 
    clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zksed.c

Modified: 
    clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index d0d747a838176..bd9202705d147 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -112,8 +112,14 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
     break;
   }
   // Zksed
-  case RISCV::BI__builtin_riscv_sm4ks:
-  case RISCV::BI__builtin_riscv_sm4ed:
+  case RISCV::BI__builtin_riscv_sm4ks: {
+    intrinsicName = "riscv.sm4ks";
+    break;
+  }
+  case RISCV::BI__builtin_riscv_sm4ed: {
+    intrinsicName = "riscv.sm4ed";
+    break;
+  }
   // Zksh
   case RISCV::BI__builtin_riscv_sm3p0:
   case RISCV::BI__builtin_riscv_sm3p1:

diff  --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zksed.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zksed.c
new file mode 100644
index 0000000000000..9cd8615927c9f
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zksed.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksed -fclangir -emit-cir %s -o - | FileCheck %s --check-prefixes=CIR
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -fclangir -emit-cir %s -o - | FileCheck %s --check-prefixes=CIR
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksed -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksed -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - | FileCheck %s --check-prefixes=LLVM
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_sm4ks(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.sm4ks" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_sm4ks(
+// LLVM: call i32 @llvm.riscv.sm4ks(i32 {{%.*}}, i32 {{%.*}}, i32 0)
+// LLVM: ret i32
+unsigned int test_builtin_sm4ks(unsigned int a, unsigned int b) {
+  return __builtin_riscv_sm4ks(a, b, 0);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_builtin_sm4ed(
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.sm4ed" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i
+// CIR: cir.return
+// LLVM-LABEL: @test_builtin_sm4ed(
+// LLVM: call i32 @llvm.riscv.sm4ed(i32 {{%.*}}, i32 {{%.*}}, i32 0)
+// LLVM: ret i32
+unsigned int test_builtin_sm4ed(unsigned int a, unsigned int b) {
+  return __builtin_riscv_sm4ed(a, b, 0);
+}