[clang] [llvm] [RISCV][MC] Support experimental Zvdota Family instructions (PR #195069)
Liao Chunyu via cfe-commits
cfe-commits at lists.llvm.org
Thu May 7 23:08:46 PDT 2026
https://github.com/ChunyuLiao updated https://github.com/llvm/llvm-project/pull/195069
>From 9986d05ebe9266a812c12851d7b3f2ed5f8fce27 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Wed, 29 Apr 2026 08:23:21 +0000
Subject: [PATCH 01/10] zvdota
---
.../Driver/print-supported-extensions-riscv.c | 4 ++
.../test/Preprocessor/riscv-target-features.c | 36 ++++++++++++++++
llvm/docs/RISCVUsage.rst | 3 ++
.../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 6 ++-
llvm/lib/Target/RISCV/RISCVFeatures.td | 30 +++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 42 +++++++++++++++++++
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++
llvm/test/CodeGen/RISCV/features-info.ll | 8 +++-
llvm/test/MC/RISCV/rvv/zvfqwdota8f.s | 40 ++++++++++++++++++
llvm/test/MC/RISCV/rvv/zvfwdota16bf.s | 27 ++++++++++++
llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s | 28 +++++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++
13 files changed, 234 insertions(+), 3 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
create mode 100644 llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
create mode 100644 llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
create mode 100644 llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 83920246d5dad..0e0519a24f619 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -252,8 +252,12 @@
// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
+// CHECK-NEXT: zvfqwdota8f 0.2 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+// CHECK-NEXT: zvfwdota16bf 0.2 'Zvfwdota16bf' (BF16 Dot-Product)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvvmm 0.1 'Zvvmm' (Integer Matrix Multiply-Accumulate)
+// CHECK-NEXT: zvqwdota16i 0.2 'Zvqwdota16i' (16-bit Integer Dot-Product)
+// CHECK-NEXT: zvqwdota8i 0.2 'Zvqwdota8i' (8-bit Integer Dot-Product)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 3882f2889eb59..5dadb9cc3dc1f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -148,6 +148,10 @@
// CHECK-NOT: __riscv_zve64d {{.*$}}
// CHECK-NOT: __riscv_zve64f {{.*$}}
// CHECK-NOT: __riscv_zve64x {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota8i {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota16i {{.*$}}
+// CHECK-NOT: __riscv_zvfqwdota8f {{.*$}}
+// CHECK-NOT: __riscv_zvfwdota16bf {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
// CHECK-NOT: __riscv_zvfh {{.*$}}
@@ -1673,6 +1677,38 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// CHECK-ZVDOT4A8I-EXT: __riscv_zvdot4a8i 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// CHECK-ZVQWDOTA8I-EXT: __riscv_zvqwdota8i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// CHECK-ZVQWDOTA16I-EXT: __riscv_zvqwdota16i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// CHECK-ZVFQWDOTA8F-EXT: __riscv_zvfqwdota8f 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// CHECK-ZVFWDOTA16BF-EXT: __riscv_zvfwdota16bf 2000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvzip0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2c8805f5fe796..3b0a792911fb1 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -353,6 +353,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvdot4a8i``
LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__.
+``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvvfqwdota8f``
+ LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__.
+
``experimental-smpmpmt``
LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index b381b8f7147fc..456f119440aba 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -225,7 +225,11 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
// above.
if (!RISCVVType::isValidVType(Imm) ||
(RISCVVType::isAltFmt(Imm) &&
- !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+ !(STI.hasFeature(RISCV::FeatureStdExtZvqwdota8i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvqwdota16i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfwdota16bf) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfqwdota8f) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
STI.hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||
(Imm >> 9) != 0) {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b905870a482ff..92c5b96efc88c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -690,6 +690,36 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
AssemblerPredicate<(all_of FeatureStdExtZvabd),
"'Zvabd' (Vector Absolute Difference)">;
+def FeatureStdExtZvqwdota8i
+ : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product", [FeatureStdExtZve32x]>;
+def HasStdExtZvqwdota8i : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product)">;
+
+def FeatureStdExtZvqwdota16i
+ : RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product", [FeatureStdExtZve64x]>;
+def HasStdExtZvqwdota16i : Predicate<"Subtarget->hasStdExtZvqwdota16i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota16i),
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+
+def HasStdExtZvqwdota8iOrZvqwdota16i
+ : Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i() ">,
+ AssemblerPredicate<(any_of FeatureStdExtZvqwdota8i, FeatureStdExtZvqwdota16i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product) or "
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+
+def FeatureStdExtZvfwdota16bf
+ : RISCVExperimentalExtension<0, 2, "BF16 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfwdota16bf : Predicate<"Subtarget->hasStdExtZvfwdota16bf()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfwdota16bf),
+ "'Zvfwdota16bf' (BF16 Dot-Product)">;
+
+def FeatureStdExtZvfqwdota8f
+ : RISCVExperimentalExtension<0, 2, "OCP FP8 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfqwdota8f : Predicate<"Subtarget->hasStdExtZvfqwdota8f()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
+ "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
+
def FeatureStdExtZvfbfa
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 3295d18a2d352..e58319095916b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2352,6 +2352,7 @@ include "RISCVInstrInfoZk.td"
// Vector
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvabd.td"
+include "RISCVInstrInfoZvdota.td"
include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoZvdot4a8i.td"
include "RISCVInstrInfoZvfofp8min.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
new file mode 100644
index 0000000000000..69bb4025fa065
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -0,0 +1,42 @@
+//===-- RISCVInstrInfoZvqwdotZvbdot.td - 'ZvqwdotZvbdot' instructions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'ZvqwdotZvbdot'.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Definitions
+//===----------------------------------------------------------------------===//
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs2, vs1, vm
+class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $vs1$vm"> {
+ let Inst{6-0} = OPC_OP_VE.Value;
+}
+}
+let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i],
+ Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx4 in {
+ def VQWDOTAU_VV : ZvdotVALUVV<0b100110, OPIVV, "vqwdotau.vv">;
+ def VQWDOTAS_VV : ZvdotVALUVV<0b100111, OPIVV, "vqwdotas.vv">;
+} // Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i]
+
+let Predicates = [HasStdExtZvfqwdota8f],
+ Constraints = "@earlyclobber $vd",
+ mayRaiseFPException = true, DestEEW = EEWSEWx4 in {
+ def VFQWDOTA_VV : ZvdotVALUVV<0b010110, OPFVV, "vfqwdota.vv">;
+ def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b010111, OPFVV, "vfqwdota.alt.vv">;
+} // Predicates = [HasStdExtZvfqwdota8f]
+
+let Predicates = [HasStdExtZvfwdota16bf],
+ Constraints = "@earlyclobber $vd",
+ mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
+ def VFWDOTA_VV : ZvdotVALUVV<0b010100, OPFVV, "vfwdota.vv">;
+} // Predicates = [HasStdExtZvfwdota16bf]
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9da6766692e99..234088444323d 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -267,6 +267,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV64ZVDOT4A8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota8i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota16i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA16I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfwdota16bf %s -o - | FileCheck --check-prefix=RV64ZVFWDOTA16BF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfqwdota8f %s -o - | FileCheck --check-prefix=RV64ZVFQWDOTA8F %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvzip %s -o - | FileCheck --check-prefix=RV64ZVZIP %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s
@@ -588,6 +592,10 @@
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
+; RV64ZVQWDOTA8I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwdota8i0p2"
+; RV64ZVQWDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwdota16i0p2"
+; RV64ZVFWDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwdota16bf0p2_zvl32b1p0"
+; RV64ZVFQWDOTA8F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfqwdota8f0p2_zvl32b1p0"
; RV64ZVZIP: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 92e033cb90dc9..e9864d14e6545 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -38,9 +38,13 @@
; CHECK-NEXT: experimental-zvdot4a8i - 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers).
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
-; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
+; CHECK-NEXT: experimental-zvfqwdota8f - 'Zvfqwdota8f' (OCP FP8 Dot-Product).
+; CHECK-NEXT: experimental-zvfwdota16bf - 'Zvfwdota16bf' (BF16 Dot-Product).
+; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
+; CHECK-NEXT: experimental-zvqwdota16i - 'Zvqwdota16i' (16-bit Integer Dot-Product).
+; CHECK-NEXT: experimental-zvqwdota8i - 'Zvqwdota8i' (8-bit Integer Dot-Product).
; CHECK-NEXT: experimental-zvvmm - 'Zvvmm' (Integer Matrix Multiply-Accumulate).
-; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
+; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).
; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available.
; CHECK-NEXT: fusion-add-load - Enable ADD(.UW) + load macrofusion.
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
new file mode 100644
index 0000000000000..818b50ed0bd55
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfqwdota8f --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vfqwdota.vv v10, v9, v8
+# CHECK-INST: vfqwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5a941577 <unknown>
+
+vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 58941577 <unknown>
+
+vfqwdota.alt.vv v10, v9, v8
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5e941577 <unknown>
+
+vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5c]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5c941577 <unknown>
+
diff --git a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
new file mode 100644
index 0000000000000..354f7a6a94f82
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfwdota16bf --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vfwdota.vv v10, v9, v8
+# CHECK-INST: vfwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
+# CHECK-UNKNOWN: 52941577 <unknown>
+
+vfwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
+# CHECK-UNKNOWN: 50941577 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
new file mode 100644
index 0000000000000..0a2636bacc5b7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvqwdota8i --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vqwdotau.vv v10, v9, v8
+# CHECK-INST: vqwdotau.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x05,0x94,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
+# CHECK-UNKNOWN: 9a940577 <unknown>
+
+vqwdotau.vv v10, v9, v8, v0.t
+# CHECK-INST: vqwdotau.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x05,0x94,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
+# CHECK-UNKNOWN: 98940577 <unknown>
+
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index e96e2d9d462dc..48babfbdc8d54 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1383,7 +1383,11 @@ Experimental extensions
zvdot4a8i 0.1
zvfbfa 0.1
zvfofp8min 0.2
+ zvfqwdota8f 0.2
+ zvfwdota16bf 0.2
zvkgs 0.7
+ zvqwdota16i 0.2
+ zvqwdota8i 0.2
zvvmm 0.1
zvzip 0.1
smpmpmt 0.6
>From 8f7d49d2dbe6b0ec5212f125dfe1cd4b888c4ec5 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Wed, 6 May 2026 03:35:37 +0000
Subject: [PATCH 02/10] fix error and dependent extension
---
clang/test/Preprocessor/riscv-target-features.c | 12 ++++++------
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 10 +++++-----
llvm/test/CodeGen/RISCV/attributes.ll | 6 +++---
llvm/test/MC/RISCV/rvv/zvfqwdota8f.s | 16 ++++++++--------
llvm/test/MC/RISCV/rvv/zvfwdota16bf.s | 16 ++++++++--------
5 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 5dadb9cc3dc1f..8249f7f2aaa14 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1686,26 +1686,26 @@
// CHECK-ZVQWDOTA8I-EXT: __riscv_zvqwdota8i 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvqwdota16i0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvqwdota16i0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
// CHECK-ZVQWDOTA16I-EXT: __riscv_zvqwdota16i 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -march=rv32i_zve32f_zvfqwdota8f0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -march=rv64i_zve32f_zvfqwdota8f0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
// CHECK-ZVFQWDOTA8F-EXT: __riscv_zvfqwdota8f 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -march=rv32i_zve32f_zvfwdota16bf0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -march=rv64i_zve32f_zvfwdota16bf0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
// CHECK-ZVFWDOTA16BF-EXT: __riscv_zvfwdota16bf 2000{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
index 69bb4025fa065..6cc0dcd79932d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoZvqwdotZvbdot.td - 'ZvqwdotZvbdot' instructions ------*- tablegen -*-===//
+//===-- RISCVInstrInfoZvdota.td - 'Zvdota' instructions ----*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
///
-/// This file describes the RISC-V instructions for 'ZvqwdotZvbdot'.
+/// This file describes the RISC-V instructions for 'Zvdota'.
///
//===----------------------------------------------------------------------===//
@@ -31,12 +31,12 @@ let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i],
let Predicates = [HasStdExtZvfqwdota8f],
Constraints = "@earlyclobber $vd",
mayRaiseFPException = true, DestEEW = EEWSEWx4 in {
- def VFQWDOTA_VV : ZvdotVALUVV<0b010110, OPFVV, "vfqwdota.vv">;
- def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b010111, OPFVV, "vfqwdota.alt.vv">;
+ def VFQWDOTA_VV : ZvdotVALUVV<0b100110, OPFVV, "vfqwdota.vv">;
+ def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b100111, OPFVV, "vfqwdota.alt.vv">;
} // Predicates = [HasStdExtZvfqwdota8f]
let Predicates = [HasStdExtZvfwdota16bf],
Constraints = "@earlyclobber $vd",
mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
- def VFWDOTA_VV : ZvdotVALUVV<0b010100, OPFVV, "vfwdota.vv">;
+ def VFWDOTA_VV : ZvdotVALUVV<0b100100, OPFVV, "vfwdota.vv">;
} // Predicates = [HasStdExtZvfwdota16bf]
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 234088444323d..02344b0570b48 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -268,9 +268,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV64ZVDOT4A8I %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota8i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA8I %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota16i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA16I %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfwdota16bf %s -o - | FileCheck --check-prefix=RV64ZVFWDOTA16BF %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfqwdota8f %s -o - | FileCheck --check-prefix=RV64ZVFQWDOTA8F %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvqwdota16i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA16I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32f -mattr=+experimental-zvfwdota16bf %s -o - | FileCheck --check-prefix=RV64ZVFWDOTA16BF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32f -mattr=+experimental-zvfqwdota8f %s -o - | FileCheck --check-prefix=RV64ZVFQWDOTA8F %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvzip %s -o - | FileCheck --check-prefix=RV64ZVZIP %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
index 818b50ed0bd55..f7821c92ce371 100644
--- a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
+++ b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
@@ -16,25 +16,25 @@ vsetvli a2, a0, e8alt, m1, ta, ma
vfqwdota.vv v10, v9, v8
# CHECK-INST: vfqwdota.vv v10, v9, v8
-# CHECK-ENCODING: [0x77,0x15,0x94,0x5a]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9a]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 5a941577 <unknown>
+# CHECK-UNKNOWN: 9a941577 <unknown>
vfqwdota.vv v10, v9, v8, v0.t
# CHECK-INST: vfqwdota.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x77,0x15,0x94,0x58]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x98]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 58941577 <unknown>
+# CHECK-UNKNOWN: 98941577 <unknown>
vfqwdota.alt.vv v10, v9, v8
# CHECK-INST: vfqwdota.alt.vv v10, v9, v8
-# CHECK-ENCODING: [0x77,0x15,0x94,0x5e]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9e]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 5e941577 <unknown>
+# CHECK-UNKNOWN: 9e941577 <unknown>
vfqwdota.alt.vv v10, v9, v8, v0.t
# CHECK-INST: vfqwdota.alt.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x77,0x15,0x94,0x5c]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9c]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 5c941577 <unknown>
+# CHECK-UNKNOWN: 9c941577 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
index 354f7a6a94f82..ae6ceb9d962f9 100644
--- a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
+++ b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
@@ -8,20 +8,20 @@
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vsetvli a2, a0, e8alt, m1, ta, ma
-# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
-# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+vsetvli a2, a0, e16alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e16alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 1c057657 <unknown>
+# CHECK-UNKNOWN: 1c857657 <unknown>
vfwdota.vv v10, v9, v8
# CHECK-INST: vfwdota.vv v10, v9, v8
-# CHECK-ENCODING: [0x77,0x15,0x94,0x52]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x92]
# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
-# CHECK-UNKNOWN: 52941577 <unknown>
+# CHECK-UNKNOWN: 92941577 <unknown>
vfwdota.vv v10, v9, v8, v0.t
# CHECK-INST: vfwdota.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x77,0x15,0x94,0x50]
+# CHECK-ENCODING: [0x77,0x15,0x94,0x90]
# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
-# CHECK-UNKNOWN: 50941577 <unknown>
+# CHECK-UNKNOWN: 90941577 <unknown>
>From e1b0464b47866d7ff4c2779e42b5c6aa66b16eeb Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Wed, 6 May 2026 07:07:30 +0000
Subject: [PATCH 03/10] fix ci error
---
clang/test/Driver/print-supported-extensions-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 0e0519a24f619..6d54e91a70cbf 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -255,9 +255,9 @@
// CHECK-NEXT: zvfqwdota8f 0.2 'Zvfqwdota8f' (OCP FP8 Dot-Product)
// CHECK-NEXT: zvfwdota16bf 0.2 'Zvfwdota16bf' (BF16 Dot-Product)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
-// CHECK-NEXT: zvvmm 0.1 'Zvvmm' (Integer Matrix Multiply-Accumulate)
// CHECK-NEXT: zvqwdota16i 0.2 'Zvqwdota16i' (16-bit Integer Dot-Product)
// CHECK-NEXT: zvqwdota8i 0.2 'Zvqwdota8i' (8-bit Integer Dot-Product)
+// CHECK-NEXT: zvvmm 0.1 'Zvvmm' (Integer Matrix Multiply-Accumulate)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
>From dcc40dbc4c5529abc201f93142d257141e6feba3 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Wed, 6 May 2026 08:49:55 +0000
Subject: [PATCH 04/10] address comment
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 32 +++++++++++--------
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 7 ++--
2 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 92c5b96efc88c..5adcdffa14433 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -691,22 +691,26 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
"'Zvabd' (Vector Absolute Difference)">;
def FeatureStdExtZvqwdota8i
- : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product", [FeatureStdExtZve32x]>;
-def HasStdExtZvqwdota8i : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
- AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
- "'Zvqwdota8i' (8-bit Integer Dot-Product)">;
+ : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product",
+ [FeatureStdExtZve32x]>;
+def HasStdExtZvqwdota8i
+ : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product)">;
def FeatureStdExtZvqwdota16i
- : RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product", [FeatureStdExtZve64x]>;
-def HasStdExtZvqwdota16i : Predicate<"Subtarget->hasStdExtZvqwdota16i()">,
- AssemblerPredicate<(all_of FeatureStdExtZvqwdota16i),
- "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+ : RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product",
+ [FeatureStdExtZve64x]>;
+def HasStdExtZvqwdota16i
+ : Predicate<"Subtarget->hasStdExtZvqwdota16i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota16i),
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
def HasStdExtZvqwdota8iOrZvqwdota16i
- : Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i() ">,
- AssemblerPredicate<(any_of FeatureStdExtZvqwdota8i, FeatureStdExtZvqwdota16i),
- "'Zvqwdota8i' (8-bit Integer Dot-Product) or "
- "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+ : Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvqwdota8i, FeatureStdExtZvqwdota16i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product) or "
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
def FeatureStdExtZvfwdota16bf
: RISCVExperimentalExtension<0, 2, "BF16 Dot-Product", [FeatureStdExtZve32f]>;
@@ -717,8 +721,8 @@ def HasStdExtZvfwdota16bf : Predicate<"Subtarget->hasStdExtZvfwdota16bf()">,
def FeatureStdExtZvfqwdota8f
: RISCVExperimentalExtension<0, 2, "OCP FP8 Dot-Product", [FeatureStdExtZve32f]>;
def HasStdExtZvfqwdota8f : Predicate<"Subtarget->hasStdExtZvfqwdota8f()">,
- AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
- "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
+ AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
+ "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
def FeatureStdExtZvfbfa
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
index 6cc0dcd79932d..4a2a8f53bc462 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -17,11 +17,14 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// op vd, vs2, vs1, vm
class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd),
- (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
- opcodestr, "$vd, $vs2, $vs1$vm"> {
+ (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $vs1$vm"> {
let Inst{6-0} = OPC_OP_VE.Value;
+ let Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb";
+ let VS1VS2Constraint = WidenV;
}
}
+
let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i],
Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx4 in {
def VQWDOTAU_VV : ZvdotVALUVV<0b100110, OPIVV, "vqwdotau.vv">;
>From 32e5e98fe485162402901a663851eba7b328ee07 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 7 May 2026 01:52:17 +0000
Subject: [PATCH 05/10] delete used, add more ext and use Vrgather
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 ++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 --------
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 2 +-
3 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index cbf3d0f518ac8..e9a40498caa5e 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2431,6 +2431,10 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvqwdota8i) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvqwdota16i) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvfwdota16bf) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvfqwdota8f) ||
STI->hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
STI->hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))
return Error(
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 5adcdffa14433..ea886e2b40bf8 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -693,18 +693,10 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
def FeatureStdExtZvqwdota8i
: RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product",
[FeatureStdExtZve32x]>;
-def HasStdExtZvqwdota8i
- : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
- AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
- "'Zvqwdota8i' (8-bit Integer Dot-Product)">;
def FeatureStdExtZvqwdota16i
: RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product",
[FeatureStdExtZve64x]>;
-def HasStdExtZvqwdota16i
- : Predicate<"Subtarget->hasStdExtZvqwdota16i()">,
- AssemblerPredicate<(all_of FeatureStdExtZvqwdota16i),
- "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
def HasStdExtZvqwdota8iOrZvqwdota16i
: Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i()">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
index 4a2a8f53bc462..f96e65e72538b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -21,7 +21,7 @@ class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
opcodestr, "$vd, $vs2, $vs1$vm"> {
let Inst{6-0} = OPC_OP_VE.Value;
let Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb";
- let VS1VS2Constraint = WidenV;
+ let VS1VS2Constraint = Vrgather;
}
}
>From e21f4f3596aea41e8c0ddf7dd17c16078723ba2e Mon Sep 17 00:00:00 2001
From: Liao Chunyu <liaochunyu126 at 126.com>
Date: Thu, 7 May 2026 09:58:29 +0800
Subject: [PATCH 06/10] Update llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
Co-authored-by: Brandon Wu <songwu0813 at gmail.com>
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
index f96e65e72538b..ed1eec013266f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -16,7 +16,7 @@
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// op vd, vs2, vs1, vm
class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
- : RVInstVV<funct6, opv, (outs VR:$vd),
+ : RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1$vm"> {
let Inst{6-0} = OPC_OP_VE.Value;
>From 2e15ee3174c7ee50b5c1d6dd6ac04bc53c438df5 Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 7 May 2026 02:20:20 +0000
Subject: [PATCH 07/10] fix ci error for last commit
---
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
index ed1eec013266f..f40cb4f8d7824 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -17,7 +17,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// op vd, vs2, vs1, vm
class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
- (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
+ (ins VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1$vm"> {
let Inst{6-0} = OPC_OP_VE.Value;
let Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb";
@@ -25,21 +25,18 @@ class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
}
}
-let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i],
- Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx4 in {
+let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i], DestEEW = EEWSEWx4 in {
def VQWDOTAU_VV : ZvdotVALUVV<0b100110, OPIVV, "vqwdotau.vv">;
def VQWDOTAS_VV : ZvdotVALUVV<0b100111, OPIVV, "vqwdotas.vv">;
} // Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i]
let Predicates = [HasStdExtZvfqwdota8f],
- Constraints = "@earlyclobber $vd",
mayRaiseFPException = true, DestEEW = EEWSEWx4 in {
def VFQWDOTA_VV : ZvdotVALUVV<0b100110, OPFVV, "vfqwdota.vv">;
def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b100111, OPFVV, "vfqwdota.alt.vv">;
} // Predicates = [HasStdExtZvfqwdota8f]
let Predicates = [HasStdExtZvfwdota16bf],
- Constraints = "@earlyclobber $vd",
mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
def VFWDOTA_VV : ZvdotVALUVV<0b100100, OPFVV, "vfwdota.vv">;
} // Predicates = [HasStdExtZvfwdota16bf]
>From 5fb7c55b2aa636c622b1e776928516275d70779f Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 7 May 2026 03:39:35 +0000
Subject: [PATCH 08/10] delete unknown and aligned
---
llvm/test/CodeGen/RISCV/features-info.ll | 12 ++++++------
llvm/test/MC/RISCV/rvv/zvfqwdota8f.s | 7 -------
llvm/test/MC/RISCV/rvv/zvfwdota16bf.s | 5 -----
llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s | 6 ------
4 files changed, 6 insertions(+), 24 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index e9864d14e6545..06f8c3d511f29 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -38,13 +38,13 @@
; CHECK-NEXT: experimental-zvdot4a8i - 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers).
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
-; CHECK-NEXT: experimental-zvfqwdota8f - 'Zvfqwdota8f' (OCP FP8 Dot-Product).
-; CHECK-NEXT: experimental-zvfwdota16bf - 'Zvfwdota16bf' (BF16 Dot-Product).
-; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
-; CHECK-NEXT: experimental-zvqwdota16i - 'Zvqwdota16i' (16-bit Integer Dot-Product).
-; CHECK-NEXT: experimental-zvqwdota8i - 'Zvqwdota8i' (8-bit Integer Dot-Product).
+; CHECK-NEXT: experimental-zvfqwdota8f - 'Zvfqwdota8f' (OCP FP8 Dot-Product).
+; CHECK-NEXT: experimental-zvfwdota16bf - 'Zvfwdota16bf' (BF16 Dot-Product).
+; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
+; CHECK-NEXT: experimental-zvqwdota16i - 'Zvqwdota16i' (16-bit Integer Dot-Product).
+; CHECK-NEXT: experimental-zvqwdota8i - 'Zvqwdota8i' (8-bit Integer Dot-Product).
; CHECK-NEXT: experimental-zvvmm - 'Zvvmm' (Integer Matrix Multiply-Accumulate).
-; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
+; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).
; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available.
; CHECK-NEXT: fusion-add-load - Enable ADD(.UW) + load macrofusion.
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
index f7821c92ce371..31140a9c4fb3a 100644
--- a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
+++ b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
@@ -5,36 +5,29 @@
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfqwdota8f --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsetvli a2, a0, e8alt, m1, ta, ma
# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 1c057657 <unknown>
vfqwdota.vv v10, v9, v8
# CHECK-INST: vfqwdota.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x15,0x94,0x9a]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 9a941577 <unknown>
vfqwdota.vv v10, v9, v8, v0.t
# CHECK-INST: vfqwdota.vv v10, v9, v8, v0.t
# CHECK-ENCODING: [0x77,0x15,0x94,0x98]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 98941577 <unknown>
vfqwdota.alt.vv v10, v9, v8
# CHECK-INST: vfqwdota.alt.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x15,0x94,0x9e]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 9e941577 <unknown>
vfqwdota.alt.vv v10, v9, v8, v0.t
# CHECK-INST: vfqwdota.alt.vv v10, v9, v8, v0.t
# CHECK-ENCODING: [0x77,0x15,0x94,0x9c]
# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
-# CHECK-UNKNOWN: 9c941577 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
index ae6ceb9d962f9..e1ff3c3d6d0ac 100644
--- a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
+++ b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
@@ -5,23 +5,18 @@
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfwdota16bf --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsetvli a2, a0, e16alt, m1, ta, ma
# CHECK-INST: vsetvli a2, a0, e16alt, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x85,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 1c857657 <unknown>
vfwdota.vv v10, v9, v8
# CHECK-INST: vfwdota.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x15,0x94,0x92]
# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
-# CHECK-UNKNOWN: 92941577 <unknown>
vfwdota.vv v10, v9, v8, v0.t
# CHECK-INST: vfwdota.vv v10, v9, v8, v0.t
# CHECK-ENCODING: [0x77,0x15,0x94,0x90]
# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
-# CHECK-UNKNOWN: 90941577 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
index 0a2636bacc5b7..2cebc3702af34 100644
--- a/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
+++ b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
@@ -5,24 +5,18 @@
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvqwdota8i --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsetvli a2, a0, e8alt, m1, ta, ma
# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 1c057657 <unknown>
vqwdotau.vv v10, v9, v8
# CHECK-INST: vqwdotau.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x05,0x94,0x9a]
# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
-# CHECK-UNKNOWN: 9a940577 <unknown>
vqwdotau.vv v10, v9, v8, v0.t
# CHECK-INST: vqwdotau.vv v10, v9, v8, v0.t
# CHECK-ENCODING: [0x77,0x05,0x94,0x98]
# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
-# CHECK-UNKNOWN: 98940577 <unknown>
-
>From 0a2d62d8054b1ff143d2a7e9254fc263c7368f5e Mon Sep 17 00:00:00 2001
From: Liao Chunyu <chunyu at iscas.ac.cn>
Date: Thu, 7 May 2026 05:36:40 +0000
Subject: [PATCH 09/10] indent
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ea886e2b40bf8..b6979908a0488 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -708,13 +708,13 @@ def FeatureStdExtZvfwdota16bf
: RISCVExperimentalExtension<0, 2, "BF16 Dot-Product", [FeatureStdExtZve32f]>;
def HasStdExtZvfwdota16bf : Predicate<"Subtarget->hasStdExtZvfwdota16bf()">,
AssemblerPredicate<(all_of FeatureStdExtZvfwdota16bf),
- "'Zvfwdota16bf' (BF16 Dot-Product)">;
+ "'Zvfwdota16bf' (BF16 Dot-Product)">;
def FeatureStdExtZvfqwdota8f
: RISCVExperimentalExtension<0, 2, "OCP FP8 Dot-Product", [FeatureStdExtZve32f]>;
def HasStdExtZvfqwdota8f : Predicate<"Subtarget->hasStdExtZvfqwdota8f()">,
AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
- "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
+ "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
def FeatureStdExtZvfbfa
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
>From 9cd323101557e62d9b584bc8bce2aa14b67df8da Mon Sep 17 00:00:00 2001
From: Liao Chunyu <liaochunyu126 at 126.com>
Date: Fri, 8 May 2026 14:08:33 +0800
Subject: [PATCH 10/10] Update llvm/docs/RISCVUsage.rst
Co-authored-by: Brandon Wu <songwu0813 at gmail.com>
---
llvm/docs/RISCVUsage.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 3b0a792911fb1..f3f1be7260dc5 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -353,7 +353,7 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvdot4a8i``
LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__.
-``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvvfqwdota8f``
+``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvfqwdota8f``
LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__.
``experimental-smpmpmt``
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