[clang] [llvm] [RISCV] Add support for quadruple-precision floating point ABIs (PR #195166)

[Gábor Spaits via cfe-commits]

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@@ -143,6 +151,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
+  if (Subtarget.hasStdExtQ())
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spaits wrote:

Or wait, it has worked before. It shouldn't need all this extra code to work after. Maybe I am messing up something in the calling conv? Or maybe, because I have added the line you are referring to will make SDag want to construct an actual hardware fp128 from the GPRs and that is causing the issue?

https://github.com/llvm/llvm-project/pull/195166