[clang] [llvm] [RISCV][MC] Support experimental Zvdota Family instructions (PR #195069)

[Brandon Wu via cfe-commits]

================
@@ -690,6 +690,36 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
                      AssemblerPredicate<(all_of FeatureStdExtZvabd),
                                         "'Zvabd' (Vector Absolute Difference)">;
 
+def FeatureStdExtZvqwdota8i
+    : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product", [FeatureStdExtZve32x]>;
+def HasStdExtZvqwdota8i : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
+                            AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
----------------
4vtomat wrote:

I think it should be indented

https://github.com/llvm/llvm-project/pull/195069