[clang] [llvm] [SelectionDAG][NVPTX] support expanding target intrinsics; implement for `nvvm.{fmax/fmin}` (PR #194783)
Princeton Ferro via cfe-commits
cfe-commits at lists.llvm.org
Sat May 2 22:55:01 PDT 2026
https://github.com/Prince781 updated https://github.com/llvm/llvm-project/pull/194783
>From 28dad3aa0da281d810ba5cd3069de9c9404b0c1c Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Mon, 27 Apr 2026 05:39:46 -0700
Subject: [PATCH 01/13] [SelectionDAG][NVPTX] support expanding target
intrinsics; implement for @nvvm.{fmax/fmin}
Adds a new feature in SelectionDAG for auto-expansion of user-defined
intrinsics. This allows targets to define scalar operations in a generic
way with vector overloads. The target has to register expansion with
setIntrinsicAction(IntrinsicID, Expand).
We implement this feature end-to-end for @nvvm.{fmax/fmin}.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 46 +++++
llvm/include/llvm/IR/IntrinsicsNVVM.td | 19 +-
llvm/include/llvm/IR/NVVMIntrinsicUtils.h | 93 +++------
llvm/lib/Analysis/ConstantFolding.cpp | 130 ++++++-------
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 +-
.../CodeGen/SelectionDAG/LegalizeTypes.cpp | 5 +-
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 128 +++++++++++++
llvm/lib/IR/AutoUpgrade.cpp | 48 -----
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 16 ++
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 181 +++++-------------
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 72 ++-----
.../math-intrins-sm80-ptx70-instcombine.ll | 12 +-
13 files changed, 363 insertions(+), 394 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 9b0bfa111f2d5..ce8bca3383832 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1299,6 +1299,33 @@ class LLVM_ABI TargetLoweringBase {
return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
}
+ /// Same as getOperationAction(), but for an intrinsic.
+ std::optional<LegalizeAction> getIntrinsicAction(Intrinsic::ID ID,
+ EVT VT) const {
+ if (VT.isExtended())
+ return Expand;
+ auto Key = std::make_pair(VT.getSimpleVT().SimpleTy, ID);
+ if (auto It = IntrinsicActions.find(Key); It != IntrinsicActions.end())
+ return It->second;
+ return std::nullopt;
+ }
+
+ LegalizeAction getOperationAction(const SDNode *N, EVT VT) const {
+ switch (N->getOpcode()) {
+ case ISD::INTRINSIC_VOID:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_WO_CHAIN: {
+ unsigned ConstIdx = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
+ if (auto Action =
+ getIntrinsicAction(N->getConstantOperandVal(ConstIdx), VT))
+ return *Action;
+ }
+ [[fallthrough]];
+ default:
+ return getOperationAction(N->getOpcode(), VT);
+ }
+ }
+
/// Custom method defined by each target to indicate if an operation which
/// may require a scale is supported natively by the target.
/// If not, the operation is illegal.
@@ -2717,6 +2744,20 @@ class LLVM_ABI TargetLoweringBase {
setOperationAction(Ops, VT, Action);
}
+ void setIntrinsicAction(Intrinsic::ID ID, MVT VT, LegalizeAction Action) {
+ IntrinsicActions[{VT.SimpleTy, ID}] = Action;
+ }
+ void setIntrinsicAction(ArrayRef<Intrinsic::ID> IDs, MVT VT,
+ LegalizeAction Action) {
+ for (auto ID : IDs)
+ setIntrinsicAction(ID, VT, Action);
+ }
+ void setIntrinsicAction(ArrayRef<Intrinsic::ID> IDs, ArrayRef<MVT> VTs,
+ LegalizeAction Action) {
+ for (auto VT : VTs)
+ setIntrinsicAction(IDs, VT, Action);
+ }
+
/// Indicate that the specified load with extension does not work with the
/// specified type and indicate what to do about it.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
@@ -3852,6 +3893,11 @@ class LLVM_ABI TargetLoweringBase {
/// non-legal value types are not described here.
LegalizeAction OpActions[MVT::VALUETYPE_SIZE][ISD::BUILTIN_OP_END];
+ /// Like OpActions but for intrinsics. Entries are optional. Will defer to
+ /// OpActions for the ISD intrinsic wrapper if not present.
+ SmallDenseMap<std::pair<MVT::SimpleValueType, Intrinsic::ID>, LegalizeAction>
+ IntrinsicActions;
+
/// For each load extension type and each value type, keep a LegalizeAction
/// that indicates how instruction selection should deal with a load of a
/// specific value type and extension type. Uses 4-bits to store the action
diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td
index cc245d4e17f5c..c6a903ae4327a 100644
--- a/llvm/include/llvm/IR/IntrinsicsNVVM.td
+++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td
@@ -1314,26 +1314,11 @@ let TargetPrefix = "nvvm" in {
let IntrProperties = [IntrNoMem, IntrSpeculatable, Commutative,
IntrNoCreateUndefOrPoison] in {
foreach operation = ["min", "max"] in {
- def int_nvvm_f # operation # _d : NVVMBuiltin,
- DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty]>;
-
foreach variant = ["", "_xorsign_abs"] in {
foreach nan = ["", "_nan"] in {
foreach ftz = ["", "_ftz"] in {
- def int_nvvm_f # operation # ftz # nan # variant # _f : NVVMBuiltin,
- DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty]>;
-
- def int_nvvm_f # operation # ftz # nan # variant # _f16 :
- DefaultAttrsIntrinsic<[llvm_half_ty], [llvm_half_ty, llvm_half_ty]>;
-
- def int_nvvm_f # operation # ftz # nan # variant # _f16x2 :
- DefaultAttrsIntrinsic<[llvm_v2f16_ty], [llvm_v2f16_ty, llvm_v2f16_ty]>;
-
- def int_nvvm_f # operation # ftz # nan # variant # _bf16 : NVVMBuiltin,
- DefaultAttrsIntrinsic<[llvm_bfloat_ty], [llvm_bfloat_ty, llvm_bfloat_ty]>;
-
- def int_nvvm_f # operation # ftz # nan # variant # _bf16x2 : NVVMBuiltin,
- DefaultAttrsIntrinsic<[llvm_v2bf16_ty], [llvm_v2bf16_ty, llvm_v2bf16_ty]>;
+ def int_nvvm_f # operation # ftz # nan # variant : NVVMBuiltin,
+ DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
} // ftz
} // nan
} // variant
diff --git a/llvm/include/llvm/IR/NVVMIntrinsicUtils.h b/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
index 067290e57245a..80f2ddc92107c 100644
--- a/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
+++ b/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
@@ -383,87 +383,48 @@ GetFPToIntegerRoundingMode(Intrinsic::ID IntrinsicID) {
inline bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID) {
switch (IntrinsicID) {
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
return true;
-
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_d:
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_nan_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f:
- return false;
}
llvm_unreachable("Checking FTZ flag for invalid fmin/fmax intrinsic");
}
inline bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID) {
switch (IntrinsicID) {
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_nan_f:
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
return true;
-
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_d:
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f:
- return false;
}
llvm_unreachable("Checking NaN flag for invalid fmin/fmax intrinsic");
}
inline bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID) {
switch (IntrinsicID) {
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
+
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_xorsign_abs:
return true;
-
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_nan_f:
-
- case Intrinsic::nvvm_fmin_d:
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_nan_f:
- return false;
}
llvm_unreachable("Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
}
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index e035cd1bc1ac0..a5561373b166a 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -1894,26 +1894,24 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
case Intrinsic::x86_avx512_cvttsd2usi64:
// NVVM FMax intrinsics
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
// NVVM FMin intrinsics
- case Intrinsic::nvvm_fmin_d:
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_nan_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f:
+ case Intrinsic::nvvm_fmin:
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_xorsign_abs:
// NVVM float/double to int32/uint32 conversion intrinsics
case Intrinsic::nvvm_f2i_rm:
@@ -3433,32 +3431,30 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
case Intrinsic::minimum:
case Intrinsic::maximumnum:
case Intrinsic::minimumnum:
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmin_d:
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmin:
// If one argument is undef, return the other argument.
if (IsOp0Undef)
return Operands[1];
if (IsOp1Undef)
return Operands[0];
- break;
+ [[fallthrough]];
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_nan_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
+
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_xorsign_abs:
// If one arg is undef, the other arg can be returned only if it is
// constant, as we may need to flush it to sign-preserving zero or
// canonicalize the NaN.
@@ -3538,28 +3534,25 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
case Intrinsic::maximumnum:
return ConstantFP::get(Ty, maximumnum(Op1V, Op2V));
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
-
- case Intrinsic::nvvm_fmin_d:
- case Intrinsic::nvvm_fmin_f:
- case Intrinsic::nvvm_fmin_ftz_f:
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_nan_f:
- case Intrinsic::nvvm_fmin_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmin_xorsign_abs_f: {
-
- bool ShouldCanonicalizeNaNs = !(IntrinsicID == Intrinsic::nvvm_fmax_d ||
- IntrinsicID == Intrinsic::nvvm_fmin_d);
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
+
+ case Intrinsic::nvvm_fmin:
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_xorsign_abs: {
+
+ bool ShouldCanonicalizeNaNs = !Ty->isDoubleTy();
bool IsFTZ = nvvm::FMinFMaxShouldFTZ(IntrinsicID);
bool IsNaNPropagating = nvvm::FMinFMaxPropagatesNaNs(IntrinsicID);
bool IsXorSignAbs = nvvm::FMinFMaxIsXorSignAbs(IntrinsicID);
@@ -3576,15 +3569,14 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
bool IsFMax = false;
switch (IntrinsicID) {
- case Intrinsic::nvvm_fmax_d:
- case Intrinsic::nvvm_fmax_f:
- case Intrinsic::nvvm_fmax_ftz_f:
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_ftz_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_nan_f:
- case Intrinsic::nvvm_fmax_nan_xorsign_abs_f:
- case Intrinsic::nvvm_fmax_xorsign_abs_f:
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
IsFMax = true;
break;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9e8e0a684f2f6..e1d261d773155 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1296,7 +1296,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
Action = TLI.getCustomOperationAction(*Node);
} else {
- Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
+ Action = TLI.getOperationAction(Node, Node->getValueType(0));
}
break;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 74b81572b6692..2ba677876760b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -922,7 +922,7 @@ SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
/// illegal ResNo in that case.
bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) {
// See if the target wants to custom lower this node.
- if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
+ if (TLI.getOperationAction(N, VT) != TargetLowering::Custom)
return false;
SmallVector<SDValue, 8> Results;
@@ -944,12 +944,11 @@ bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) {
return true;
}
-
/// Widen the node's results with custom code provided by the target and return
/// "true", or do nothing and return "false".
bool DAGTypeLegalizer::CustomWidenLowerNode(SDNode *N, EVT VT) {
// See if the target wants to custom lower this node.
- if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
+ if (TLI.getOperationAction(N, VT) != TargetLowering::Custom)
return false;
SmallVector<SDValue, 8> Results;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 89698a2c77123..ed4c5f3d8cde7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -863,6 +863,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ScalarizeVecRes_FIX(SDNode *N);
SDValue ScalarizeVecRes_UnaryOpWithTwoResults(SDNode *N, unsigned ResNo);
+ SDValue ScalarizeVecRes_INTRINSIC(SDNode *N);
+
// Vector Operand Scalarization: <1 x ty> -> ty.
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecOp_BITCAST(SDNode *N);
@@ -902,6 +904,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
+ bool CanSplitVectorIntrinsic(const SDNode *N);
+
/// Split mask operator of a VP intrinsic.
std::pair<SDValue, SDValue> SplitMask(SDValue Mask);
@@ -965,6 +969,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void SplitVecRes_VP_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_GET_ACTIVE_LANE_MASK(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_INTRINSIC(SDNode *N, SDValue &Lo, SDValue &Hi);
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 856590ed2624f..fe61ec0e66572 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -256,6 +256,12 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UDIVFIXSAT:
R = ScalarizeVecRes_FIX(N);
break;
+
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
+ R = ScalarizeVecRes_INTRINSIC(N);
+ break;
}
// If R is null, the sub-method took care of registering the result.
@@ -829,6 +835,89 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_IS_FPCLASS(SDNode *N) {
return DAG.getNode(ExtendCode, DL, ResultVT, Res);
}
+bool DAGTypeLegalizer::CanSplitVectorIntrinsic(const SDNode *N) {
+ unsigned ConstIdx = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
+ unsigned IntrinsicID = N->getConstantOperandVal(ConstIdx);
+
+ // Analyze the intrinsic signature. If there is one unique vector type used
+ // between all the operands and results, we can split.
+ SmallVector<Intrinsic::IITDescriptor> Descriptors;
+ Intrinsic::getIntrinsicInfoTableEntries(IntrinsicID, Descriptors);
+
+ auto GetOpVT = [&](unsigned I) -> EVT {
+ switch (N->getOpcode()) {
+ case ISD::INTRINSIC_WO_CHAIN:
+ return I < N->getNumValues()
+ ? N->getValueType(I)
+ : N->getOperand(I - N->getNumValues()).getValueType();
+ case ISD::INTRINSIC_W_CHAIN:
+ return I < N->getNumValues() - 1
+ ? N->getValueType(I)
+ : N->getOperand(I - N->getNumValues() + 1).getValueType();
+ case ISD::INTRINSIC_VOID:
+ return N->getOperand(I).getValueType();
+ default:
+ llvm_unreachable("Expected intrinsic opcode");
+ }
+ };
+
+ std::optional<EVT> SeenVecVT;
+ for (auto [I, OperandDesc] : enumerate(Descriptors)) {
+ EVT OpVT = GetOpVT(I);
+
+ if (!OpVT.isVector())
+ continue;
+
+ // All vector types must be equal to VT. Furthermore, we must see at most
+ // one T that is not a LLVMMatchType for VT, otherwise we can't be sure how
+ // to split this intrinsic.
+ switch (OperandDesc.Kind) {
+ case Intrinsic::IITDescriptor::Overloaded:
+ if (OperandDesc.getOverloadKind() ==
+ Intrinsic::IITDescriptor::AK_MatchType)
+ if (OperandDesc.getOverloadIndex() != 0) {
+ DAG.getContext()->emitError(
+ Twine("Can't expand. Intrinsic must have a single overloaded "
+ "vector type: ") +
+ N->getOperationName(&DAG));
+ return false;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (SeenVecVT && OpVT != SeenVecVT) {
+ DAG.getContext()->emitError(
+ Twine("Can't expand. Intrinsic has a non-overloaded vector type: ") +
+ N->getOperationName(&DAG));
+ return false;
+ }
+
+ SeenVecVT = OpVT;
+ }
+
+ return true;
+}
+
+SDValue DAGTypeLegalizer::ScalarizeVecRes_INTRINSIC(SDNode *N) {
+ if (!CanSplitVectorIntrinsic(N))
+ return SDValue();
+
+ SmallVector<SDValue> ScalarOps(map_range(N->ops(), [&](const SDValue &Op) {
+ if (EVT VT = Op.getValueType(); VT.isVector())
+ return DAG.getExtractVectorElt(SDLoc(N), VT.getVectorElementType(), Op,
+ 0);
+ return Op;
+ }));
+
+ SmallVector<EVT> ScalarVTs(map_range(N->values(), [](EVT VT) {
+ return VT.isVector() ? VT.getVectorElementType() : VT;
+ }));
+
+ return DAG.getNode(N->getOpcode(), SDLoc(N), ScalarVTs, ScalarOps);
+}
+
//===----------------------------------------------------------------------===//
// Operand Vector Scalarization <1 x ty> -> ty.
//===----------------------------------------------------------------------===//
@@ -1615,6 +1704,12 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::GET_ACTIVE_LANE_MASK:
SplitVecRes_GET_ACTIVE_LANE_MASK(N, Lo, Hi);
break;
+
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
+ SplitVecRes_INTRINSIC(N, Lo, Hi);
+ break;
}
// If Lo/Hi is null, the sub-method took care of registering results etc.
@@ -3669,6 +3764,39 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_INTERLEAVE(SDNode *N) {
}
}
+void DAGTypeLegalizer::SplitVecRes_INTRINSIC(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ if (!CanSplitVectorIntrinsic(N))
+ return;
+
+ SmallVector<SDValue> Operands1, Operands2;
+ for (auto [I, Op] : enumerate(N->ops())) {
+ if (auto OpVT = Op.getValueType(); OpVT.isVector()) {
+ auto [OpLeft, OpRight] = DAG.SplitVectorOperand(N, I);
+ Operands1.push_back(OpLeft);
+ Operands2.push_back(OpRight);
+ } else {
+ Operands1.push_back(Op);
+ Operands2.push_back(Op);
+ }
+ }
+
+ SmallVector<EVT> ResultVTs1, ResultVTs2;
+ for (auto [I, RVT] : enumerate(N->values())) {
+ if (RVT.isVector()) {
+ auto [VTLeft, VTRight] = DAG.GetSplitDestVTs(RVT);
+ ResultVTs1.push_back(VTLeft);
+ ResultVTs2.push_back(VTRight);
+ } else {
+ ResultVTs1.push_back(RVT);
+ ResultVTs2.push_back(RVT);
+ }
+ }
+
+ Lo = DAG.getNode(N->getOpcode(), SDLoc(N), ResultVTs1, Operands1);
+ Hi = DAG.getNode(N->getOpcode(), SDLoc(N), ResultVTs2, Operands2);
+}
+
//===----------------------------------------------------------------------===//
// Operand Vector Splitting
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 433300ec63585..8aee5a03e8bc4 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -1195,54 +1195,6 @@ static Intrinsic::ID shouldUpgradeNVPTXBF16Intrinsic(StringRef Name) {
.Case("relu.bf16x2", Intrinsic::nvvm_fma_rn_relu_bf16x2)
.Default(Intrinsic::not_intrinsic);
- if (Name.consume_front("fmax."))
- return StringSwitch<Intrinsic::ID>(Name)
- .Case("bf16", Intrinsic::nvvm_fmax_bf16)
- .Case("bf16x2", Intrinsic::nvvm_fmax_bf16x2)
- .Case("ftz.bf16", Intrinsic::nvvm_fmax_ftz_bf16)
- .Case("ftz.bf16x2", Intrinsic::nvvm_fmax_ftz_bf16x2)
- .Case("ftz.nan.bf16", Intrinsic::nvvm_fmax_ftz_nan_bf16)
- .Case("ftz.nan.bf16x2", Intrinsic::nvvm_fmax_ftz_nan_bf16x2)
- .Case("ftz.nan.xorsign.abs.bf16",
- Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_bf16)
- .Case("ftz.nan.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_bf16x2)
- .Case("ftz.xorsign.abs.bf16", Intrinsic::nvvm_fmax_ftz_xorsign_abs_bf16)
- .Case("ftz.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmax_ftz_xorsign_abs_bf16x2)
- .Case("nan.bf16", Intrinsic::nvvm_fmax_nan_bf16)
- .Case("nan.bf16x2", Intrinsic::nvvm_fmax_nan_bf16x2)
- .Case("nan.xorsign.abs.bf16", Intrinsic::nvvm_fmax_nan_xorsign_abs_bf16)
- .Case("nan.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmax_nan_xorsign_abs_bf16x2)
- .Case("xorsign.abs.bf16", Intrinsic::nvvm_fmax_xorsign_abs_bf16)
- .Case("xorsign.abs.bf16x2", Intrinsic::nvvm_fmax_xorsign_abs_bf16x2)
- .Default(Intrinsic::not_intrinsic);
-
- if (Name.consume_front("fmin."))
- return StringSwitch<Intrinsic::ID>(Name)
- .Case("bf16", Intrinsic::nvvm_fmin_bf16)
- .Case("bf16x2", Intrinsic::nvvm_fmin_bf16x2)
- .Case("ftz.bf16", Intrinsic::nvvm_fmin_ftz_bf16)
- .Case("ftz.bf16x2", Intrinsic::nvvm_fmin_ftz_bf16x2)
- .Case("ftz.nan.bf16", Intrinsic::nvvm_fmin_ftz_nan_bf16)
- .Case("ftz.nan.bf16x2", Intrinsic::nvvm_fmin_ftz_nan_bf16x2)
- .Case("ftz.nan.xorsign.abs.bf16",
- Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_bf16)
- .Case("ftz.nan.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_bf16x2)
- .Case("ftz.xorsign.abs.bf16", Intrinsic::nvvm_fmin_ftz_xorsign_abs_bf16)
- .Case("ftz.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmin_ftz_xorsign_abs_bf16x2)
- .Case("nan.bf16", Intrinsic::nvvm_fmin_nan_bf16)
- .Case("nan.bf16x2", Intrinsic::nvvm_fmin_nan_bf16x2)
- .Case("nan.xorsign.abs.bf16", Intrinsic::nvvm_fmin_nan_xorsign_abs_bf16)
- .Case("nan.xorsign.abs.bf16x2",
- Intrinsic::nvvm_fmin_nan_xorsign_abs_bf16x2)
- .Case("xorsign.abs.bf16", Intrinsic::nvvm_fmin_xorsign_abs_bf16)
- .Case("xorsign.abs.bf16x2", Intrinsic::nvvm_fmin_xorsign_abs_bf16x2)
- .Default(Intrinsic::not_intrinsic);
-
if (Name.consume_front("neg."))
return StringSwitch<Intrinsic::ID>(Name)
.Case("bf16", Intrinsic::nvvm_neg_bf16)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 83d02fa31b577..a8ceca5613dcd 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -1124,6 +1124,22 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(ISD::INTRINSIC_WO_CHAIN,
{MVT::i32, MVT::i128, MVT::v4f32, MVT::Other}, Custom);
+ // Enable automatic expansion for intrinsics:
+ // * nvvm.{fmin/fmax}
+ for (auto VT : MVT::fp_fixedlen_vector_valuetypes()) {
+ setIntrinsicAction(
+ {Intrinsic::nvvm_fmax, Intrinsic::nvvm_fmax_ftz,
+ Intrinsic::nvvm_fmax_ftz_nan, Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs,
+ Intrinsic::nvvm_fmax_ftz_xorsign_abs, Intrinsic::nvvm_fmax_nan,
+ Intrinsic::nvvm_fmax_nan_xorsign_abs, Intrinsic::nvvm_fmax_xorsign_abs,
+ Intrinsic::nvvm_fmin, Intrinsic::nvvm_fmin_ftz,
+ Intrinsic::nvvm_fmin_ftz_nan, Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs,
+ Intrinsic::nvvm_fmin_ftz_xorsign_abs, Intrinsic::nvvm_fmin_nan,
+ Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ Intrinsic::nvvm_fmin_xorsign_abs},
+ VT, Expand);
+ }
+
// Custom lowering for bswap
setOperationAction(ISD::BSWAP, {MVT::i16, MVT::i32, MVT::i64, MVT::v2i16},
Custom);
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 1a3420ac6a7c7..4839e33539279 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -1262,30 +1262,30 @@ foreach op = ["test_wait", "try_wait"] in {
// max(0.0, min(x, 1.0)) is 1.0 while sat(x) is 0.
// Same story for fmax, fmin.
-def : Pat<(int_nvvm_fmin_f fpimm_1,
- (int_nvvm_fmax_f fpimm_0, f32:$a)),
+def : Pat<(f32 (int_nvvm_fmin (f32 fpimm_1),
+ (f32 (int_nvvm_fmax (f32 fpimm_0), f32:$a)))),
(CVT_f32_f32 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_f fpimm_1,
- (int_nvvm_fmax_f f32:$a, fpimm_0)),
+def : Pat<(f32 (int_nvvm_fmin (f32 fpimm_1),
+ (f32 (int_nvvm_fmax f32:$a, (f32 fpimm_0))))),
(CVT_f32_f32 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_f
- (int_nvvm_fmax_f fpimm_0, f32:$a), fpimm_1),
+def : Pat<(f32 (int_nvvm_fmin
+ (f32 (int_nvvm_fmax (f32 fpimm_0), f32:$a)), (f32 fpimm_1))),
(CVT_f32_f32 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_f
- (int_nvvm_fmax_f f32:$a, fpimm_0), fpimm_1),
+def : Pat<(f32 (int_nvvm_fmin
+ (f32 (int_nvvm_fmax f32:$a, (f32 fpimm_0))), (f32 fpimm_1))),
(CVT_f32_f32 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_d fpimm_1,
- (int_nvvm_fmax_d fpimm_0, f64:$a)),
+def : Pat<(f64 (int_nvvm_fmin (f64 fpimm_1),
+ (f64 (int_nvvm_fmax (f64 fpimm_0), f64:$a)))),
(CVT_f64_f64 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_d fpimm_1,
- (int_nvvm_fmax_d f64:$a, fpimm_0)),
+def : Pat<(f64 (int_nvvm_fmin (f64 fpimm_1),
+ (f64 (int_nvvm_fmax f64:$a, (f64 fpimm_0))))),
(CVT_f64_f64 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_d
- (int_nvvm_fmax_d fpimm_0, f64:$a), fpimm_1),
+def : Pat<(f64 (int_nvvm_fmin
+ (f64 (int_nvvm_fmax (f64 fpimm_0), f64:$a)), (f64 fpimm_1))),
(CVT_f64_f64 $a, CvtSAT)>;
-def : Pat<(int_nvvm_fmin_d
- (int_nvvm_fmax_d f64:$a, fpimm_0), fpimm_1),
+def : Pat<(f64 (int_nvvm_fmin
+ (f64 (int_nvvm_fmax f64:$a, (f64 fpimm_0))), (f64 fpimm_1))),
(CVT_f64_f64 $a, CvtSAT)>;
@@ -1310,6 +1310,14 @@ class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
[(set t_regclass:$dst, (IntOP s0_regclass:$src0, s1_regclass:$src1))]>,
Requires<Preds>;
+class F_MATH_2_TYPED<string OpcStr, RegTyInfo t_ty,
+ RegTyInfo s0_ty, RegTyInfo s1_ty, Intrinsic IntOP,
+ list<Predicate> Preds = []>
+ : BasicNVPTXInst<(outs t_ty.RC:$dst), (ins s0_ty.RC:$src0, s1_ty.RC:$src1),
+ OpcStr,
+ [(set t_ty.Ty:$dst, (IntOP s0_ty.Ty:$src0, s1_ty.Ty:$src1))]>,
+ Requires<Preds>;
+
class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
NVPTXRegClass s0_regclass, NVPTXRegClass s1_regclass,
NVPTXRegClass s2_regclass, Intrinsic IntOP, list<Predicate> Preds = []>
@@ -1348,132 +1356,43 @@ def INT_PM_EVENT_MASK : BasicNVPTXInst<(outs),
// Min Max
//
-def : Pat<(int_nvvm_fmin_f f32:$a, f32:$b), (MIN_f32_rr $a, $b, NoFTZ)>;
-def : Pat<(int_nvvm_fmin_ftz_f f32:$a, f32:$b), (MIN_f32_rr $a, $b, FTZ)>;
+def : Pat<(f32 (int_nvvm_fmin f32:$a, f32:$b)), (MIN_f32_rr $a, $b, NoFTZ)>;
+def : Pat<(f32 (int_nvvm_fmin_ftz f32:$a, f32:$b)), (MIN_f32_rr $a, $b, FTZ)>;
let Predicates = [hasPTX<70>, hasSM<80>] in {
- def : Pat<(int_nvvm_fmin_nan_f f32:$a, f32:$b), (MIN_NAN_f32_rr $a, $b, NoFTZ)>;
- def : Pat<(int_nvvm_fmin_ftz_nan_f f32:$a, f32:$b), (MIN_NAN_f32_rr $a, $b, FTZ)>;
+ def : Pat<(f32 (int_nvvm_fmin_nan f32:$a, f32:$b)), (MIN_NAN_f32_rr $a, $b, NoFTZ)>;
+ def : Pat<(f32 (int_nvvm_fmin_ftz_nan f32:$a, f32:$b)), (MIN_NAN_f32_rr $a, $b, FTZ)>;
}
-def INT_NVVM_FMIN_XORSIGN_ABS_F :
- F_MATH_2<"min.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F :
- F_MATH_2<"min.ftz.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_ftz_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMIN_NAN_XORSIGN_ABS_F :
- F_MATH_2<"min.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_nan_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F :
- F_MATH_2<"min.ftz.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_ftz_nan_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-
-
-def : Pat<(int_nvvm_fmax_f f32:$a, f32:$b), (MAX_f32_rr $a, $b, NoFTZ)>;
-def : Pat<(int_nvvm_fmax_ftz_f f32:$a, f32:$b), (MAX_f32_rr $a, $b, FTZ)>;
+def : Pat<(f32 (int_nvvm_fmax f32:$a, f32:$b)), (MAX_f32_rr $a, $b, NoFTZ)>;
+def : Pat<(f32 (int_nvvm_fmax_ftz f32:$a, f32:$b)), (MAX_f32_rr $a, $b, FTZ)>;
let Predicates = [hasPTX<70>, hasSM<80>] in {
- def : Pat<(int_nvvm_fmax_nan_f f32:$a, f32:$b), (MAX_NAN_f32_rr $a, $b, NoFTZ)>;
- def : Pat<(int_nvvm_fmax_ftz_nan_f f32:$a, f32:$b), (MAX_NAN_f32_rr $a, $b, FTZ)>;
-}
-
-def INT_NVVM_FMAX_XORSIGN_ABS_F :
- F_MATH_2<"max.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F :
- F_MATH_2<"max.ftz.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_ftz_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMAX_NAN_XORSIGN_ABS_F :
- F_MATH_2<"max.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_nan_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-def INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F :
- F_MATH_2<"max.ftz.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_ftz_nan_xorsign_abs_f,
- [hasPTX<72>, hasSM<86>]>;
-
-def : Pat<(int_nvvm_fmin_d f64:$a, f64:$b), (MIN_f64_rr $a, $b)>;
-def : Pat<(int_nvvm_fmax_d f64:$a, f64:$b), (MAX_f64_rr $a, $b)>;
+ def : Pat<(f32 (int_nvvm_fmax_nan f32:$a, f32:$b)), (MAX_NAN_f32_rr $a, $b, NoFTZ)>;
+ def : Pat<(f32 (int_nvvm_fmax_ftz_nan f32:$a, f32:$b)), (MAX_NAN_f32_rr $a, $b, FTZ)>;
+}
+
+def : Pat<(f64 (int_nvvm_fmin f64:$a, f64:$b)), (MIN_f64_rr $a, $b)>;
+def : Pat<(f64 (int_nvvm_fmax f64:$a, f64:$b)), (MAX_f64_rr $a, $b)>;
//
-// Min Max f16, f16x2, bf16, bf16x2
+// Min Max f16, f16x2, bf16, bf16x2, f32, f64
//
-class MIN_MAX_TUPLE<string V, Intrinsic I, NVPTXRegClass RC,
- list<Predicate> Preds = [hasPTX<70>, hasSM<80>]> {
- string Variant = V;
- Intrinsic Intr = I;
- NVPTXRegClass RegClass = RC;
- list<Predicate> Predicates = Preds;
-}
-
multiclass MIN_MAX<string IntName> {
- foreach P = [
- MIN_MAX_TUPLE<"_f16", !if(!eq(IntName, "min"), int_nvvm_fmin_f16,
- int_nvvm_fmax_f16), B16>,
- MIN_MAX_TUPLE<"_ftz_f16", !if(!eq(IntName, "min"), int_nvvm_fmin_ftz_f16,
- int_nvvm_fmax_ftz_f16), B16>,
- MIN_MAX_TUPLE<"_NaN_f16", !if(!eq(IntName, "min"), int_nvvm_fmin_nan_f16,
- int_nvvm_fmax_nan_f16), B16>,
- MIN_MAX_TUPLE<"_ftz_NaN_f16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_nan_f16, int_nvvm_fmax_ftz_nan_f16), B16>,
- MIN_MAX_TUPLE<"_xorsign_abs_f16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_xorsign_abs_f16, int_nvvm_fmax_xorsign_abs_f16),
- B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_ftz_xorsign_abs_f16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_xorsign_abs_f16, int_nvvm_fmax_ftz_xorsign_abs_f16),
- B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_NaN_xorsign_abs_f16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_xorsign_abs_f16, int_nvvm_fmax_nan_xorsign_abs_f16),
- B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_ftz_NaN_xorsign_abs_f16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_nan_xorsign_abs_f16,
- int_nvvm_fmax_ftz_nan_xorsign_abs_f16), B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_f16x2", !if(!eq(IntName, "min"), int_nvvm_fmin_f16x2,
- int_nvvm_fmax_f16x2), B32>,
- MIN_MAX_TUPLE<"_ftz_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_f16x2, int_nvvm_fmax_ftz_f16x2), B32>,
- MIN_MAX_TUPLE<"_NaN_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_f16x2, int_nvvm_fmax_nan_f16x2), B32>,
- MIN_MAX_TUPLE<"_ftz_NaN_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_nan_f16x2, int_nvvm_fmax_ftz_nan_f16x2), B32>,
- MIN_MAX_TUPLE<"_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_xorsign_abs_f16x2, int_nvvm_fmax_xorsign_abs_f16x2),
- B32, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_ftz_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_xorsign_abs_f16x2, int_nvvm_fmax_ftz_xorsign_abs_f16x2),
- B32, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_NaN_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_xorsign_abs_f16x2, int_nvvm_fmax_nan_xorsign_abs_f16x2),
- B32, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_ftz_NaN_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
- int_nvvm_fmax_ftz_nan_xorsign_abs_f16x2),
- B32, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_bf16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_bf16, int_nvvm_fmax_bf16), B16>,
- MIN_MAX_TUPLE<"_NaN_bf16", !if(!eq(IntName, "min"), int_nvvm_fmin_nan_bf16,
- int_nvvm_fmax_nan_bf16), B16>,
- MIN_MAX_TUPLE<"_xorsign_abs_bf16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_xorsign_abs_bf16, int_nvvm_fmax_xorsign_abs_bf16),
- B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_NaN_xorsign_abs_bf16", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_xorsign_abs_bf16, int_nvvm_fmax_nan_xorsign_abs_bf16),
- B16, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_bf16x2", !if(!eq(IntName, "min"), int_nvvm_fmin_bf16x2,
- int_nvvm_fmax_bf16x2), B32>,
- MIN_MAX_TUPLE<"_NaN_bf16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_bf16x2, int_nvvm_fmax_nan_bf16x2), B32>,
- MIN_MAX_TUPLE<"_xorsign_abs_bf16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_xorsign_abs_bf16x2, int_nvvm_fmax_xorsign_abs_bf16x2),
- B32, [hasPTX<72>, hasSM<86>]>,
- MIN_MAX_TUPLE<"_NaN_xorsign_abs_bf16x2", !if(!eq(IntName, "min"),
- int_nvvm_fmin_nan_xorsign_abs_bf16x2,
- int_nvvm_fmax_nan_xorsign_abs_bf16x2),
- B32, [hasPTX<72>, hasSM<86>]>] in {
- def P.Variant : F_MATH_2<!strconcat(
- IntName, !subst("_", ".", P.Variant)),
- P.RegClass, P.RegClass, P.RegClass, P.Intr, P.Predicates>;
- }
+ foreach variant = ["", "_xorsign_abs"] in {
+ foreach nan = ["", "_NaN"] in {
+ foreach ftz = ["", "_ftz"] in {
+ foreach rt = [F16RT, F16X2RT, BF16RT, BF16X2RT, F32RT, F64RT] in {
+ def ftz # nan # variant # "_" # rt.Ty
+ : F_MATH_2_TYPED<IntName # !subst("_", ".", ftz # nan # variant) # "." # rt.PtxType,
+ rt, rt, rt,
+ !cast<Intrinsic>("int_nvvm_f" # IntName # ftz # !tolower(nan) # variant),
+ !if(!eq(variant, "_xorsign_abs"), [hasPTX<72>, hasSM<86>], [])>;
+ } // vt
+ } // ftz
+ } // nan
+ } // variant
}
defm INT_NVVM_FMIN : MIN_MAX<"min">;
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index a491d0ed4a912..dd15d59b251af 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -174,9 +174,11 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
: Special(Special), FtzRequirement(FtzReq) {}
};
+ Type *RetTy = II->getFunctionType()->getReturnType();
+
// Try to generate a SimplifyAction describing how to replace our
// IntrinsicInstr with target-generic LLVM IR.
- const SimplifyAction Action = [II]() -> SimplifyAction {
+ const SimplifyAction Action = [II, RetTy]() -> SimplifyAction {
switch (II->getIntrinsicID()) {
// NVVM intrinsics that map directly to LLVM intrinsics.
case Intrinsic::nvvm_ceil_d:
@@ -209,58 +211,22 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
return {Intrinsic::fma, FTZ_MustBeOff, true};
case Intrinsic::nvvm_fma_rn_bf16x2:
return {Intrinsic::fma, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmax_d:
- return {Intrinsic::maximumnum, FTZ_Any};
- case Intrinsic::nvvm_fmax_f:
- return {Intrinsic::maximumnum, FTZ_MustBeOff};
- case Intrinsic::nvvm_fmax_ftz_f:
- return {Intrinsic::maximumnum, FTZ_MustBeOn};
- case Intrinsic::nvvm_fmax_nan_f:
- return {Intrinsic::maximum, FTZ_MustBeOff};
- case Intrinsic::nvvm_fmax_ftz_nan_f:
- return {Intrinsic::maximum, FTZ_MustBeOn};
- case Intrinsic::nvvm_fmax_f16:
- return {Intrinsic::maximumnum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmax_ftz_f16:
- return {Intrinsic::maximumnum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmax_f16x2:
- return {Intrinsic::maximumnum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmax_ftz_f16x2:
- return {Intrinsic::maximumnum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmax_nan_f16:
- return {Intrinsic::maximum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmax_ftz_nan_f16:
- return {Intrinsic::maximum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmax_nan_f16x2:
- return {Intrinsic::maximum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmax_ftz_nan_f16x2:
- return {Intrinsic::maximum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmin_d:
- return {Intrinsic::minimumnum, FTZ_Any};
- case Intrinsic::nvvm_fmin_f:
- return {Intrinsic::minimumnum, FTZ_MustBeOff};
- case Intrinsic::nvvm_fmin_ftz_f:
- return {Intrinsic::minimumnum, FTZ_MustBeOn};
- case Intrinsic::nvvm_fmin_nan_f:
- return {Intrinsic::minimum, FTZ_MustBeOff};
- case Intrinsic::nvvm_fmin_ftz_nan_f:
- return {Intrinsic::minimum, FTZ_MustBeOn};
- case Intrinsic::nvvm_fmin_f16:
- return {Intrinsic::minimumnum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmin_ftz_f16:
- return {Intrinsic::minimumnum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmin_f16x2:
- return {Intrinsic::minimumnum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmin_ftz_f16x2:
- return {Intrinsic::minimumnum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmin_nan_f16:
- return {Intrinsic::minimum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmin_ftz_nan_f16:
- return {Intrinsic::minimum, FTZ_MustBeOn, true};
- case Intrinsic::nvvm_fmin_nan_f16x2:
- return {Intrinsic::minimum, FTZ_MustBeOff, true};
- case Intrinsic::nvvm_fmin_ftz_nan_f16x2:
- return {Intrinsic::minimum, FTZ_MustBeOn, true};
+ case Intrinsic::nvvm_fmax:
+ return {Intrinsic::maximumnum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmax_ftz:
+ return {Intrinsic::maximumnum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmax_nan:
+ return {Intrinsic::maximum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ return {Intrinsic::maximum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmin:
+ return {Intrinsic::minimumnum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmin_ftz:
+ return {Intrinsic::minimumnum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmin_nan:
+ return {Intrinsic::minimum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ return {Intrinsic::minimum, FTZ_MustBeOn, RetTy->isHalfTy()};
case Intrinsic::nvvm_sqrt_rn_d:
return {Intrinsic::sqrt, FTZ_Any};
case Intrinsic::nvvm_sqrt_f:
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
index e96fe5dfcba38..26fe9afb81119 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
@@ -73,7 +73,7 @@ define <2 x half> @fmin_ftz_f16x2(<2 x half> %0, <2 x half> %1) #0 {
; CHECK-LABEL: fmin_ftz_f16x2_no_attr
define <2 x half> @fmin_ftz_f16x2_no_attr(<2 x half> %0, <2 x half> %1) {
; CHECK-NOT: @llvm.minimumnum.v2f16
- ; CHECK: @llvm.nvvm.fmin.ftz.f16x2
+ ; CHECK: @llvm.nvvm.fmin.ftz.v2f16
%res = call <2 x half> @llvm.nvvm.fmin.ftz.f16x2(<2 x half> %0, <2 x half> %1)
ret <2 x half> %res
}
@@ -96,7 +96,7 @@ define float @fmin_ftz_nan_f(float %0, float %1) #1 {
; CHECK-LABEL: fmin_ftz_nan_f_no_attr
define float @fmin_ftz_nan_f_no_attr(float %0, float %1) {
- ; CHECK: @llvm.nvvm.fmin.ftz.nan.f
+ ; CHECK: @llvm.nvvm.fmin.ftz.nan.f32
; CHECK-NOT: @llvm.minimum.f32
%res = call float @llvm.nvvm.fmin.ftz.nan.f(float %0, float %1)
ret float %res
@@ -145,7 +145,7 @@ define <2 x half> @fmin_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) #0 {
; CHECK-LABEL: fmin_ftz_nan_f16x2_no_attr
define <2 x half> @fmin_ftz_nan_f16x2_no_attr(<2 x half> %0, <2 x half> %1) {
; CHECK-NOT: @llvm.minimum.v2f16
- ; CHECK: @llvm.nvvm.fmin.ftz.nan.f16x2
+ ; CHECK: @llvm.nvvm.fmin.ftz.nan.v2f16
%res = call <2 x half> @llvm.nvvm.fmin.ftz.nan.f16x2(<2 x half> %0, <2 x half> %1)
ret <2 x half> %res
}
@@ -193,7 +193,7 @@ define <2 x half> @fmax_ftz_f16x2(<2 x half> %0, <2 x half> %1) #0 {
; CHECK-LABEL: fmax_ftz_f16x2_no_attr
define <2 x half> @fmax_ftz_f16x2_no_attr(<2 x half> %0, <2 x half> %1) {
; CHECK-NOT: @llvm.maximumnum.v2f16
- ; CHECK: @llvm.nvvm.fmax.ftz.f16x2
+ ; CHECK: @llvm.nvvm.fmax.ftz.v2f16
%res = call <2 x half> @llvm.nvvm.fmax.ftz.f16x2(<2 x half> %0, <2 x half> %1)
ret <2 x half> %res
}
@@ -216,7 +216,7 @@ define float @fmax_ftz_nan_f(float %0, float %1) #1 {
; CHECK-LABEL: fmax_ftz_nan_f_no_attr
define float @fmax_ftz_nan_f_no_attr(float %0, float %1) {
- ; CHECK: @llvm.nvvm.fmax.ftz.nan.f
+ ; CHECK: @llvm.nvvm.fmax.ftz.nan.f32
; CHECK-NOT: @llvm.maximum.f32
%res = call float @llvm.nvvm.fmax.ftz.nan.f(float %0, float %1)
ret float %res
@@ -265,7 +265,7 @@ define <2 x half> @fmax_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) #0 {
; CHECK-LABEL: fmax_ftz_nan_f16x2_no_attr
define <2 x half> @fmax_ftz_nan_f16x2_no_attr(<2 x half> %0, <2 x half> %1) {
; CHECK-NOT: @llvm.maximum.v2f16
- ; CHECK: @llvm.nvvm.fmax.ftz.nan.f16x2
+ ; CHECK: @llvm.nvvm.fmax.ftz.nan.v2f16
%res = call <2 x half> @llvm.nvvm.fmax.ftz.nan.f16x2(<2 x half> %0, <2 x half> %1)
ret <2 x half> %res
}
>From 97f51a64fb9470921551ea011939ac036a27683c Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Tue, 28 Apr 2026 22:34:45 -0700
Subject: [PATCH 02/13] [NVPTX] Fix crashes and correctness bugs in FMinFMax
simplification
Three fixes for the generic nvvm_fmax/fmin intrinsics introduced in the
parent commit:
1. NVVMIntrinsicUtils.h: FMinFMaxShouldFTZ, FMinFMaxPropagatesNaNs, and
FMinFMaxIsXorSignAbs only handled the true-returning variants (ftz/nan/
xorsign_abs). The non-ftz/non-nan/non-xorsign variants (which should
return false) were missing and fell through to llvm_unreachable, causing
a crash when InstCombine constant-folded e.g. @llvm.nvvm.fmax.f64(1.0, 2.0).
2. NVPTXTargetTransformInfo.cpp: RetTy->isHalfTy() is false for <2 x half>
(a vector type). Use ScalarTy->isHalfTy() so that the correct denormal
mode attribute is checked for vectorized half operations.
3. NVPTXTargetTransformInfo.cpp: double was given FTZ_MustBeOff, which would
check the float denormal mode (broken per the FIXME comment). Since
doubles cannot be flushed to zero, FTZ_Any is correct and avoids the
broken float-attribute lookup entirely.
Add regression tests for all three fixes.
---
llvm/include/llvm/IR/NVVMIntrinsicUtils.h | 30 +++++++++
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 25 +++++---
.../math-intrins-sm80-ptx70-instcombine.ll | 63 +++++++++++++++++++
3 files changed, 110 insertions(+), 8 deletions(-)
diff --git a/llvm/include/llvm/IR/NVVMIntrinsicUtils.h b/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
index 80f2ddc92107c..3f561e7eb9c5a 100644
--- a/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
+++ b/llvm/include/llvm/IR/NVVMIntrinsicUtils.h
@@ -393,6 +393,16 @@ inline bool FMinFMaxShouldFTZ(Intrinsic::ID IntrinsicID) {
case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
return true;
+
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
+ case Intrinsic::nvvm_fmin:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_nan_xorsign_abs:
+ case Intrinsic::nvvm_fmin_xorsign_abs:
+ return false;
}
llvm_unreachable("Checking FTZ flag for invalid fmin/fmax intrinsic");
}
@@ -409,6 +419,16 @@ inline bool FMinFMaxPropagatesNaNs(Intrinsic::ID IntrinsicID) {
case Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs:
case Intrinsic::nvvm_fmin_nan_xorsign_abs:
return true;
+
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_xorsign_abs:
+ case Intrinsic::nvvm_fmax_ftz_xorsign_abs:
+ case Intrinsic::nvvm_fmin:
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_xorsign_abs:
+ case Intrinsic::nvvm_fmin_ftz_xorsign_abs:
+ return false;
}
llvm_unreachable("Checking NaN flag for invalid fmin/fmax intrinsic");
}
@@ -425,6 +445,16 @@ inline bool FMinFMaxIsXorSignAbs(Intrinsic::ID IntrinsicID) {
case Intrinsic::nvvm_fmin_nan_xorsign_abs:
case Intrinsic::nvvm_fmin_xorsign_abs:
return true;
+
+ case Intrinsic::nvvm_fmax:
+ case Intrinsic::nvvm_fmax_ftz:
+ case Intrinsic::nvvm_fmax_nan:
+ case Intrinsic::nvvm_fmax_ftz_nan:
+ case Intrinsic::nvvm_fmin:
+ case Intrinsic::nvvm_fmin_ftz:
+ case Intrinsic::nvvm_fmin_nan:
+ case Intrinsic::nvvm_fmin_ftz_nan:
+ return false;
}
llvm_unreachable("Checking XorSignAbs flag for invalid fmin/fmax intrinsic");
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index dd15d59b251af..901118fe4c9db 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -179,6 +179,7 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
// Try to generate a SimplifyAction describing how to replace our
// IntrinsicInstr with target-generic LLVM IR.
const SimplifyAction Action = [II, RetTy]() -> SimplifyAction {
+ Type *ScalarTy = RetTy->getScalarType();
switch (II->getIntrinsicID()) {
// NVVM intrinsics that map directly to LLVM intrinsics.
case Intrinsic::nvvm_ceil_d:
@@ -212,21 +213,29 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
case Intrinsic::nvvm_fma_rn_bf16x2:
return {Intrinsic::fma, FTZ_MustBeOff, true};
case Intrinsic::nvvm_fmax:
- return {Intrinsic::maximumnum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ return {Intrinsic::maximumnum,
+ ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
+ ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmax_ftz:
- return {Intrinsic::maximumnum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ return {Intrinsic::maximumnum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmax_nan:
- return {Intrinsic::maximum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ return {Intrinsic::maximum,
+ ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
+ ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmax_ftz_nan:
- return {Intrinsic::maximum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ return {Intrinsic::maximum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmin:
- return {Intrinsic::minimumnum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ return {Intrinsic::minimumnum,
+ ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
+ ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmin_ftz:
- return {Intrinsic::minimumnum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ return {Intrinsic::minimumnum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmin_nan:
- return {Intrinsic::minimum, FTZ_MustBeOff, RetTy->isHalfTy()};
+ return {Intrinsic::minimum,
+ ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
+ ScalarTy->isHalfTy()};
case Intrinsic::nvvm_fmin_ftz_nan:
- return {Intrinsic::minimum, FTZ_MustBeOn, RetTy->isHalfTy()};
+ return {Intrinsic::minimum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
case Intrinsic::nvvm_sqrt_rn_d:
return {Intrinsic::sqrt, FTZ_Any};
case Intrinsic::nvvm_sqrt_f:
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
index 26fe9afb81119..f45f2eddef90d 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
@@ -24,6 +24,11 @@ declare half @llvm.nvvm.fmax.ftz.nan.f16(half, half)
declare <2 x half> @llvm.nvvm.fmax.nan.f16x2(<2 x half>, <2 x half>)
declare <2 x half> @llvm.nvvm.fmax.ftz.nan.f16x2(<2 x half>, <2 x half>)
+declare double @llvm.nvvm.fmin.f64(double, double)
+declare double @llvm.nvvm.fmax.f64(double, double)
+declare <2 x half> @llvm.nvvm.fmin.ftz.v2f16(<2 x half>, <2 x half>)
+declare <2 x half> @llvm.nvvm.fmax.ftz.v2f16(<2 x half>, <2 x half>)
+
; f16 and f16x2 fma are available since ptx 4.2 and sm_53.
declare half @llvm.nvvm.fma.rn.f16(half, half, half)
declare half @llvm.nvvm.fma.rn.ftz.f16(half, half, half)
@@ -318,5 +323,63 @@ define <2 x half> @fma_rn_ftz_f16x2_no_attr(<2 x half> %0, <2 x half> %1, <2 x h
ret <2 x half> %res
}
+; Crash reproducer: constant-folding nvvm_fmax.f64 must not call llvm_unreachable
+; in FMinFMaxShouldFTZ (which lacked cases for the non-ftz generic IDs).
+; CHECK-LABEL: fmax_f64_const_fold
+define double @fmax_f64_const_fold() {
+ ; CHECK-NOT: @llvm.nvvm.fmax.f64
+ ; CHECK: ret double 2.000000e+00
+ %res = call double @llvm.nvvm.fmax.f64(double 1.0, double 2.0)
+ ret double %res
+}
+
+; CHECK-LABEL: fmin_f64_const_fold
+define double @fmin_f64_const_fold() {
+ ; CHECK-NOT: @llvm.nvvm.fmin.f64
+ ; CHECK: ret double 1.000000e+00
+ %res = call double @llvm.nvvm.fmin.f64(double 1.0, double 2.0)
+ ret double %res
+}
+
+; Bug: double got FTZ_MustBeOff instead of FTZ_Any. The float:preservesign
+; attribute enables FTZ for f32 only; it must not block simplification of a
+; double intrinsic (doubles can't be flushed to zero).
+; CHECK-LABEL: fmax_f64_float_ftz_attr
+define double @fmax_f64_float_ftz_attr(double %0, double %1) #1 {
+ ; CHECK-NOT: @llvm.nvvm.fmax.f64
+ ; CHECK: @llvm.maximumnum.f64
+ %res = call double @llvm.nvvm.fmax.f64(double %0, double %1)
+ ret double %res
+}
+
+; CHECK-LABEL: fmin_f64_float_ftz_attr
+define double @fmin_f64_float_ftz_attr(double %0, double %1) #1 {
+ ; CHECK-NOT: @llvm.nvvm.fmin.f64
+ ; CHECK: @llvm.minimumnum.f64
+ %res = call double @llvm.nvvm.fmin.f64(double %0, double %1)
+ ret double %res
+}
+
+; Bug: IsHalfTy was false for <2 x half> because RetTy->isHalfTy() returns
+; false for vector types. The ftz variant must consult denormal-fp-math (the
+; half attribute), not denormal-fp-math-f32 (the float attribute).
+; With float:preservesign (#1) only the f32 denormal mode is set; the half
+; denormal mode is off, so the ftz variant should NOT be simplified.
+; CHECK-LABEL: fmax_ftz_f16x2_float_attr
+define <2 x half> @fmax_ftz_f16x2_float_attr(<2 x half> %0, <2 x half> %1) #1 {
+ ; CHECK-NOT: @llvm.maximumnum.v2f16
+ ; CHECK: @llvm.nvvm.fmax.ftz.v2f16
+ %res = call <2 x half> @llvm.nvvm.fmax.ftz.v2f16(<2 x half> %0, <2 x half> %1)
+ ret <2 x half> %res
+}
+
+; CHECK-LABEL: fmin_ftz_f16x2_float_attr
+define <2 x half> @fmin_ftz_f16x2_float_attr(<2 x half> %0, <2 x half> %1) #1 {
+ ; CHECK-NOT: @llvm.minimumnum.v2f16
+ ; CHECK: @llvm.nvvm.fmin.ftz.v2f16
+ %res = call <2 x half> @llvm.nvvm.fmin.ftz.v2f16(<2 x half> %0, <2 x half> %1)
+ ret <2 x half> %res
+}
+
attributes #0 = { denormal_fpenv(preservesign) }
attributes #1 = { denormal_fpenv(float: preservesign) }
>From bcf5a80f3dd6eed9130620a808dbf7b97f18ba7f Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 02:16:51 -0700
Subject: [PATCH 03/13] [NVPTX] AutoUpgrade old fmax/fmin type-suffix intrinsic
names; fix test names
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The PR replaced type-specific intrinsics (nvvm_fmax_f, nvvm_fmax_d,
nvvm_fmax_f16x2, nvvm_fmax_bf16x2, etc.) with a single overloaded
nvvm_fmax family. The old AutoUpgrade code for bf16/bf16x2 was removed
but no entries were added for the remaining renames: .f→.f32, .d→.f64,
.f16x2→.v2f16, .bf16x2→.v2bf16.
Add AutoUpgrade entries in UpgradeIntrinsicFunction1 for all 16 fmax/fmin
× type-suffix combinations. Also update the three test files that still
referenced old intrinsic names, and remove superfluous prose comments from
the instcombine regression tests added in the previous fixup commit.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/lib/IR/AutoUpgrade.cpp | 57 +++++
.../math-intrins-sm80-ptx70-instcombine.ll | 10 -
.../InstCombine/NVPTX/nvvm-intrins.ll | 32 +--
.../InstSimplify/const-fold-nvvm-fmin-fmax.ll | 216 +++++++++---------
.../InstSimplify/disable_folding.ll | 8 +-
5 files changed, 185 insertions(+), 138 deletions(-)
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 8aee5a03e8bc4..a4e31d261c4cf 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -1660,6 +1660,63 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn,
NewFn = nullptr;
return true;
}
+
+ // Upgrade nvvm fmin/fmax type-specific intrinsics to the generic
+ // overloaded form. Old suffixes: .f -> .f32, .d -> .f64,
+ // .f16x2 -> .v2f16, .bf16x2 -> .v2bf16. (.f16 and .bf16 are unchanged.)
+ if (Name.starts_with("fmin.") || Name.starts_with("fmax.")) {
+ LLVMContext &Ctx = F->getContext();
+ Type *NewTy = nullptr;
+ StringRef Base;
+
+ if (Name.ends_with(".bf16x2")) {
+ Base = Name.drop_back(7);
+ NewTy = FixedVectorType::get(Type::getBFloatTy(Ctx), 2);
+ } else if (Name.ends_with(".f16x2")) {
+ Base = Name.drop_back(6);
+ NewTy = FixedVectorType::get(Type::getHalfTy(Ctx), 2);
+ } else if (Name.ends_with(".f")) {
+ Base = Name.drop_back(2);
+ NewTy = Type::getFloatTy(Ctx);
+ } else if (Name.ends_with(".d")) {
+ Base = Name.drop_back(2);
+ NewTy = Type::getDoubleTy(Ctx);
+ }
+
+ if (NewTy) {
+ Intrinsic::ID IID =
+ StringSwitch<Intrinsic::ID>(Base)
+ .Case("fmax", Intrinsic::nvvm_fmax)
+ .Case("fmax.ftz", Intrinsic::nvvm_fmax_ftz)
+ .Case("fmax.nan", Intrinsic::nvvm_fmax_nan)
+ .Case("fmax.ftz.nan", Intrinsic::nvvm_fmax_ftz_nan)
+ .Case("fmax.xorsign.abs", Intrinsic::nvvm_fmax_xorsign_abs)
+ .Case("fmax.ftz.xorsign.abs",
+ Intrinsic::nvvm_fmax_ftz_xorsign_abs)
+ .Case("fmax.nan.xorsign.abs",
+ Intrinsic::nvvm_fmax_nan_xorsign_abs)
+ .Case("fmax.ftz.nan.xorsign.abs",
+ Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs)
+ .Case("fmin", Intrinsic::nvvm_fmin)
+ .Case("fmin.ftz", Intrinsic::nvvm_fmin_ftz)
+ .Case("fmin.nan", Intrinsic::nvvm_fmin_nan)
+ .Case("fmin.ftz.nan", Intrinsic::nvvm_fmin_ftz_nan)
+ .Case("fmin.xorsign.abs", Intrinsic::nvvm_fmin_xorsign_abs)
+ .Case("fmin.ftz.xorsign.abs",
+ Intrinsic::nvvm_fmin_ftz_xorsign_abs)
+ .Case("fmin.nan.xorsign.abs",
+ Intrinsic::nvvm_fmin_nan_xorsign_abs)
+ .Case("fmin.ftz.nan.xorsign.abs",
+ Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs)
+ .Default(Intrinsic::not_intrinsic);
+ if (IID != Intrinsic::not_intrinsic) {
+ NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), IID,
+ {NewTy});
+ return true;
+ }
+ }
+ }
+
break; // No other 'nvvm.*'.
}
break;
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
index f45f2eddef90d..74dccd056cc63 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
@@ -323,8 +323,6 @@ define <2 x half> @fma_rn_ftz_f16x2_no_attr(<2 x half> %0, <2 x half> %1, <2 x h
ret <2 x half> %res
}
-; Crash reproducer: constant-folding nvvm_fmax.f64 must not call llvm_unreachable
-; in FMinFMaxShouldFTZ (which lacked cases for the non-ftz generic IDs).
; CHECK-LABEL: fmax_f64_const_fold
define double @fmax_f64_const_fold() {
; CHECK-NOT: @llvm.nvvm.fmax.f64
@@ -341,9 +339,6 @@ define double @fmin_f64_const_fold() {
ret double %res
}
-; Bug: double got FTZ_MustBeOff instead of FTZ_Any. The float:preservesign
-; attribute enables FTZ for f32 only; it must not block simplification of a
-; double intrinsic (doubles can't be flushed to zero).
; CHECK-LABEL: fmax_f64_float_ftz_attr
define double @fmax_f64_float_ftz_attr(double %0, double %1) #1 {
; CHECK-NOT: @llvm.nvvm.fmax.f64
@@ -360,11 +355,6 @@ define double @fmin_f64_float_ftz_attr(double %0, double %1) #1 {
ret double %res
}
-; Bug: IsHalfTy was false for <2 x half> because RetTy->isHalfTy() returns
-; false for vector types. The ftz variant must consult denormal-fp-math (the
-; half attribute), not denormal-fp-math-f32 (the float attribute).
-; With float:preservesign (#1) only the f32 denormal mode is set; the half
-; denormal mode is off, so the ftz variant should NOT be simplified.
; CHECK-LABEL: fmax_ftz_f16x2_float_attr
define <2 x half> @fmax_ftz_f16x2_float_attr(<2 x half> %0, <2 x half> %1) #1 {
; CHECK-NOT: @llvm.maximumnum.v2f16
diff --git a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
index db172c5a34cdc..bd9e995757c17 100644
--- a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
+++ b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
@@ -105,42 +105,42 @@ define float @fma_float_ftz(float %a, float %b, float %c) #0 {
; CHECK-LABEL: @fmax_double
define double @fmax_double(double %a, double %b) #0 {
; CHECK: call double @llvm.maximumnum.f64
- %ret = call double @llvm.nvvm.fmax.d(double %a, double %b)
+ %ret = call double @llvm.nvvm.fmax.f64(double %a, double %b)
ret double %ret
}
; CHECK-LABEL: @fmax_float
define float @fmax_float(float %a, float %b) #0 {
; NOFTZ: call float @llvm.maximumnum.f32
-; FTZ: call float @llvm.nvvm.fmax.f
- %ret = call float @llvm.nvvm.fmax.f(float %a, float %b)
+; FTZ: call float @llvm.nvvm.fmax.f32
+ %ret = call float @llvm.nvvm.fmax.f32(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmax_float_ftz
define float @fmax_float_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.fmax.ftz.f
+; NOFTZ: call float @llvm.nvvm.fmax.ftz.f32
; FTZ: call float @llvm.maximumnum.f32
- %ret = call float @llvm.nvvm.fmax.ftz.f(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmax.ftz.f32(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmin_double
define double @fmin_double(double %a, double %b) #0 {
; CHECK: call double @llvm.minimumnum.f64
- %ret = call double @llvm.nvvm.fmin.d(double %a, double %b)
+ %ret = call double @llvm.nvvm.fmin.f64(double %a, double %b)
ret double %ret
}
; CHECK-LABEL: @fmin_float
define float @fmin_float(float %a, float %b) #0 {
; NOFTZ: call float @llvm.minimumnum.f32
-; FTZ: call float @llvm.nvvm.fmin.f
- %ret = call float @llvm.nvvm.fmin.f(float %a, float %b)
+; FTZ: call float @llvm.nvvm.fmin.f32
+ %ret = call float @llvm.nvvm.fmin.f32(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmin_float_ftz
define float @fmin_float_ftz(float %a, float %b) #0 {
-; NOFTZ: call float @llvm.nvvm.fmin.ftz.f
+; NOFTZ: call float @llvm.nvvm.fmin.ftz.f32
; FTZ: call float @llvm.minimumnum.f32
- %ret = call float @llvm.nvvm.fmin.ftz.f(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmin.ftz.f32(float %a, float %b)
ret float %ret
}
@@ -475,12 +475,12 @@ declare float @llvm.nvvm.floor.ftz.f(float)
declare double @llvm.nvvm.fma.rn.d(double, double, double)
declare float @llvm.nvvm.fma.rn.f(float, float, float)
declare float @llvm.nvvm.fma.rn.ftz.f(float, float, float)
-declare double @llvm.nvvm.fmax.d(double, double)
-declare float @llvm.nvvm.fmax.f(float, float)
-declare float @llvm.nvvm.fmax.ftz.f(float, float)
-declare double @llvm.nvvm.fmin.d(double, double)
-declare float @llvm.nvvm.fmin.f(float, float)
-declare float @llvm.nvvm.fmin.ftz.f(float, float)
+declare double @llvm.nvvm.fmax.f64(double, double)
+declare float @llvm.nvvm.fmax.f32(float, float)
+declare float @llvm.nvvm.fmax.ftz.f32(float, float)
+declare double @llvm.nvvm.fmin.f64(double, double)
+declare float @llvm.nvvm.fmin.f32(float, float)
+declare float @llvm.nvvm.fmin.ftz.f32(float, float)
declare double @llvm.nvvm.i2d.rn(i32)
declare float @llvm.nvvm.i2f.rn(i32)
declare double @llvm.nvvm.ll2d.rn(i64)
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
index 4ab6b3cf295bf..b6c544d2fe669 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
@@ -11,7 +11,7 @@ define double @test_fmax_1_25_neg_2_d() {
; CHECK-LABEL: define double @test_fmax_1_25_neg_2_d() {
; CHECK-NEXT: ret double 1.250000e+00
;
- %res = call double @llvm.nvvm.fmax.d(double 1.25, double -2.0)
+ %res = call double @llvm.nvvm.fmax.f64(double 1.25, double -2.0)
ret double %res
}
@@ -19,7 +19,7 @@ define float @test_fmax_1_25_neg_2_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.f32(float 1.25, float -2.0)
ret float %res
}
@@ -27,7 +27,7 @@ define float @test_fmax_1_25_neg_2_ftz_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 1.25, float -2.0)
ret float %res
}
@@ -35,7 +35,7 @@ define float @test_fmax_1_25_neg_2_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_nan_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.25, float -2.0)
ret float %res
}
@@ -43,7 +43,7 @@ define float @test_fmax_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -51,7 +51,7 @@ define float @test_fmax_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -59,7 +59,7 @@ define float @test_fmax_1_25_neg_2_nan_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_nan_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 1.25, float -2.0)
ret float %res
}
@@ -67,7 +67,7 @@ define float @test_fmax_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -75,7 +75,7 @@ define float @test_fmax_1_25_neg_2_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -87,7 +87,7 @@ define double @test_fmax_pos_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_zero_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0.0)
+ %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0.0)
ret double %res
}
@@ -95,7 +95,7 @@ define float @test_fmax_pos_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -103,7 +103,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -111,7 +111,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -119,7 +119,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -127,7 +127,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -135,7 +135,7 @@ define float @test_fmax_pos_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -143,7 +143,7 @@ define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -151,7 +151,7 @@ define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -163,7 +163,7 @@ define double @test_fmax_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_neg_subnorm_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
+ %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
}
@@ -171,7 +171,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -179,7 +179,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -187,7 +187,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -195,7 +195,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -203,7 +203,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -211,7 +211,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -219,7 +219,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -227,7 +227,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -239,7 +239,7 @@ define double @test_fmax_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_nan_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
+ %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
}
@@ -247,7 +247,7 @@ define float @test_fmax_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -255,7 +255,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -263,7 +263,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -271,7 +271,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -279,7 +279,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -287,7 +287,7 @@ define float @test_fmax_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -295,7 +295,7 @@ define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -303,7 +303,7 @@ define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -315,7 +315,7 @@ define double @test_fmax_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmax_subnorm_undef_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double undef)
+ %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double undef)
ret double %res
}
@@ -323,7 +323,7 @@ define float @test_fmax_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -331,7 +331,7 @@ define float @test_fmax_subnorm_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -339,7 +339,7 @@ define float @test_fmax_subnorm_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -347,7 +347,7 @@ define float @test_fmax_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -355,7 +355,7 @@ define float @test_fmax_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -363,7 +363,7 @@ define float @test_fmax_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -371,7 +371,7 @@ define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -379,7 +379,7 @@ define float @test_fmax_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -392,7 +392,7 @@ define double @test_fmax_nan_undef_d() {
; CHECK-LABEL: define double @test_fmax_nan_undef_d() {
; CHECK-NEXT: ret double 0x7FF4444400000000
;
- %res = call double @llvm.nvvm.fmax.d(double 0x7ff4444400000000, double undef)
+ %res = call double @llvm.nvvm.fmax.f64(double 0x7ff4444400000000, double undef)
ret double %res
}
@@ -400,7 +400,7 @@ define float @test_fmax_nan_undef_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -408,7 +408,7 @@ define float @test_fmax_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -416,7 +416,7 @@ define float @test_fmax_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -424,7 +424,7 @@ define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -432,7 +432,7 @@ define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x7ffff4ff00000000, float undef)
ret float %res
}
@@ -440,7 +440,7 @@ define float @test_fmax_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -448,7 +448,7 @@ define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -456,7 +456,7 @@ define float @test_fmax_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -468,7 +468,7 @@ define double @test_fmin_1_25_neg_2_d() {
; CHECK-LABEL: define double @test_fmin_1_25_neg_2_d() {
; CHECK-NEXT: ret double -2.000000e+00
;
- %res = call double @llvm.nvvm.fmin.d(double 1.25, double -2.0)
+ %res = call double @llvm.nvvm.fmin.f64(double 1.25, double -2.0)
ret double %res
}
@@ -476,7 +476,7 @@ define float @test_fmin_1_25_neg_2_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.f32(float 1.25, float -2.0)
ret float %res
}
@@ -484,7 +484,7 @@ define float @test_fmin_1_25_neg_2_ftz_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 1.25, float -2.0)
ret float %res
}
@@ -492,7 +492,7 @@ define float @test_fmin_1_25_neg_2_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_nan_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 1.25, float -2.0)
ret float %res
}
@@ -500,7 +500,7 @@ define float @test_fmin_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -508,7 +508,7 @@ define float @test_fmin_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -516,7 +516,7 @@ define float @test_fmin_1_25_neg_2_nan_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_nan_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 1.25, float -2.0)
ret float %res
}
@@ -524,7 +524,7 @@ define float @test_fmin_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -532,7 +532,7 @@ define float @test_fmin_1_25_neg_2_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -544,7 +544,7 @@ define double @test_fmin_neg_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmin_neg_subnorm_zero_d() {
; CHECK-NEXT: ret double 0xB80FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.d(double 0xB80FFFFFC0000000, double 0.0)
+ %res = call double @llvm.nvvm.fmin.f64(double 0xB80FFFFFC0000000, double 0.0)
ret double %res
}
@@ -552,7 +552,7 @@ define float @test_fmin_neg_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -560,7 +560,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -568,7 +568,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_nan_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -576,7 +576,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -584,7 +584,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -592,7 +592,7 @@ define float @test_fmin_neg_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_nan_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -600,7 +600,7 @@ define float @test_fmin_neg_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -608,7 +608,7 @@ define float @test_fmin_neg_subnorm_zero_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -620,7 +620,7 @@ define double @test_fmin_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_neg_subnorm_d() {
; CHECK-NEXT: ret double 0xB80FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
+ %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
}
@@ -628,7 +628,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -636,7 +636,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -644,7 +644,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -652,7 +652,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -660,7 +660,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -668,7 +668,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -676,7 +676,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -684,7 +684,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -696,7 +696,7 @@ define double @test_fmin_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_nan_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
+ %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
}
@@ -704,7 +704,7 @@ define float @test_fmin_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -712,7 +712,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -720,7 +720,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -728,7 +728,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -736,7 +736,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -744,7 +744,7 @@ define float @test_fmin_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -752,7 +752,7 @@ define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -760,7 +760,7 @@ define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -772,7 +772,7 @@ define double @test_fmin_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmin_subnorm_undef_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double undef)
+ %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double undef)
ret double %res
}
@@ -780,7 +780,7 @@ define float @test_fmin_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -788,7 +788,7 @@ define float @test_fmin_subnorm_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -796,7 +796,7 @@ define float @test_fmin_subnorm_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -804,7 +804,7 @@ define float @test_fmin_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -812,7 +812,7 @@ define float @test_fmin_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -820,7 +820,7 @@ define float @test_fmin_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -828,7 +828,7 @@ define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -836,7 +836,7 @@ define float @test_fmin_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -849,7 +849,7 @@ define double @test_fmin_nan_undef_d() {
; CHECK-LABEL: define double @test_fmin_nan_undef_d() {
; CHECK-NEXT: ret double 0x7FF4444400000000
;
- %res = call double @llvm.nvvm.fmin.d(double 0x7ff4444400000000, double undef)
+ %res = call double @llvm.nvvm.fmin.f64(double 0x7ff4444400000000, double undef)
ret double %res
}
@@ -857,7 +857,7 @@ define float @test_fmin_nan_undef_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -865,7 +865,7 @@ define float @test_fmin_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -873,7 +873,7 @@ define float @test_fmin_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -881,7 +881,7 @@ define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -889,7 +889,7 @@ define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x7ffff4ff00000000, float undef)
ret float %res
}
@@ -897,7 +897,7 @@ define float @test_fmin_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -905,7 +905,7 @@ define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -913,6 +913,6 @@ define float @test_fmin_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x7fff444400000000, float undef)
ret float %res
}
diff --git a/llvm/test/Transforms/InstSimplify/disable_folding.ll b/llvm/test/Transforms/InstSimplify/disable_folding.ll
index 66adf6af1e97f..b014a20c0f4aa 100644
--- a/llvm/test/Transforms/InstSimplify/disable_folding.ll
+++ b/llvm/test/Transforms/InstSimplify/disable_folding.ll
@@ -10,10 +10,10 @@ define float @test_fmax_ftz_nan_xorsign_abs_f() {
; FOLDING_ENABLED-NEXT: ret float -2.000000e+00
;
; FOLDING_DISABLED-LABEL: define float @test_fmax_ftz_nan_xorsign_abs_f() {
-; FOLDING_DISABLED-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 1.250000e+00, float -2.000000e+00)
+; FOLDING_DISABLED-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.250000e+00, float -2.000000e+00)
; FOLDING_DISABLED-NEXT: ret float [[RES]]
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
ret float %res
}
@@ -33,10 +33,10 @@ define float @test_llvm_sin() {
; Should not be folded, even when -disable-fp-call-folding is not set, as it is marked as strictfp.
define float @test_fmax_ftz_nan_f_strictfp() {
; CHECK-LABEL: define float @test_fmax_ftz_nan_f_strictfp() {
-; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.f(float 1.250000e+00, float -2.000000e+00) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.250000e+00, float -2.000000e+00) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret float [[RES]]
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 1.25, float -2.0) #1
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.25, float -2.0) #1
ret float %res
}
>From 5c597a63be3a2a73d0d764b431e544a22ea10191 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 02:27:18 -0700
Subject: [PATCH 04/13] [NVPTX] Don't update test call sites that AutoUpgrade
already handles
AutoUpgrade converts old fmax/fmin type-suffix names (e.g. .f, .d, .f16x2)
at IR load time, so tests can keep using old names as inputs. Only the
CHECK lines that match pass output need the new mangled names. Restore
call sites and declares to old names in nvvm-intrins.ll and
disable_folding.ll; revert const-fold-nvvm-fmin-fmax.ll entirely since
its CHECK lines only test constant values, not intrinsic names.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
.../InstCombine/NVPTX/nvvm-intrins.ll | 24 +-
.../InstSimplify/const-fold-nvvm-fmin-fmax.ll | 216 +++++++++---------
.../InstSimplify/disable_folding.ll | 4 +-
3 files changed, 122 insertions(+), 122 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
index bd9e995757c17..8266c33b7d158 100644
--- a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
+++ b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
@@ -105,42 +105,42 @@ define float @fma_float_ftz(float %a, float %b, float %c) #0 {
; CHECK-LABEL: @fmax_double
define double @fmax_double(double %a, double %b) #0 {
; CHECK: call double @llvm.maximumnum.f64
- %ret = call double @llvm.nvvm.fmax.f64(double %a, double %b)
+ %ret = call double @llvm.nvvm.fmax.d(double %a, double %b)
ret double %ret
}
; CHECK-LABEL: @fmax_float
define float @fmax_float(float %a, float %b) #0 {
; NOFTZ: call float @llvm.maximumnum.f32
; FTZ: call float @llvm.nvvm.fmax.f32
- %ret = call float @llvm.nvvm.fmax.f32(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmax.f(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmax_float_ftz
define float @fmax_float_ftz(float %a, float %b) #0 {
; NOFTZ: call float @llvm.nvvm.fmax.ftz.f32
; FTZ: call float @llvm.maximumnum.f32
- %ret = call float @llvm.nvvm.fmax.ftz.f32(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmax.ftz.f(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmin_double
define double @fmin_double(double %a, double %b) #0 {
; CHECK: call double @llvm.minimumnum.f64
- %ret = call double @llvm.nvvm.fmin.f64(double %a, double %b)
+ %ret = call double @llvm.nvvm.fmin.d(double %a, double %b)
ret double %ret
}
; CHECK-LABEL: @fmin_float
define float @fmin_float(float %a, float %b) #0 {
; NOFTZ: call float @llvm.minimumnum.f32
; FTZ: call float @llvm.nvvm.fmin.f32
- %ret = call float @llvm.nvvm.fmin.f32(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmin.f(float %a, float %b)
ret float %ret
}
; CHECK-LABEL: @fmin_float_ftz
define float @fmin_float_ftz(float %a, float %b) #0 {
; NOFTZ: call float @llvm.nvvm.fmin.ftz.f32
; FTZ: call float @llvm.minimumnum.f32
- %ret = call float @llvm.nvvm.fmin.ftz.f32(float %a, float %b)
+ %ret = call float @llvm.nvvm.fmin.ftz.f(float %a, float %b)
ret float %ret
}
@@ -475,12 +475,12 @@ declare float @llvm.nvvm.floor.ftz.f(float)
declare double @llvm.nvvm.fma.rn.d(double, double, double)
declare float @llvm.nvvm.fma.rn.f(float, float, float)
declare float @llvm.nvvm.fma.rn.ftz.f(float, float, float)
-declare double @llvm.nvvm.fmax.f64(double, double)
-declare float @llvm.nvvm.fmax.f32(float, float)
-declare float @llvm.nvvm.fmax.ftz.f32(float, float)
-declare double @llvm.nvvm.fmin.f64(double, double)
-declare float @llvm.nvvm.fmin.f32(float, float)
-declare float @llvm.nvvm.fmin.ftz.f32(float, float)
+declare double @llvm.nvvm.fmax.d(double, double)
+declare float @llvm.nvvm.fmax.f(float, float)
+declare float @llvm.nvvm.fmax.ftz.f(float, float)
+declare double @llvm.nvvm.fmin.d(double, double)
+declare float @llvm.nvvm.fmin.f(float, float)
+declare float @llvm.nvvm.fmin.ftz.f(float, float)
declare double @llvm.nvvm.i2d.rn(i32)
declare float @llvm.nvvm.i2f.rn(i32)
declare double @llvm.nvvm.ll2d.rn(i64)
diff --git a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
index b6c544d2fe669..4ab6b3cf295bf 100644
--- a/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
+++ b/llvm/test/Transforms/InstSimplify/const-fold-nvvm-fmin-fmax.ll
@@ -11,7 +11,7 @@ define double @test_fmax_1_25_neg_2_d() {
; CHECK-LABEL: define double @test_fmax_1_25_neg_2_d() {
; CHECK-NEXT: ret double 1.250000e+00
;
- %res = call double @llvm.nvvm.fmax.f64(double 1.25, double -2.0)
+ %res = call double @llvm.nvvm.fmax.d(double 1.25, double -2.0)
ret double %res
}
@@ -19,7 +19,7 @@ define float @test_fmax_1_25_neg_2_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.f(float 1.25, float -2.0)
ret float %res
}
@@ -27,7 +27,7 @@ define float @test_fmax_1_25_neg_2_ftz_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 1.25, float -2.0)
ret float %res
}
@@ -35,7 +35,7 @@ define float @test_fmax_1_25_neg_2_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_nan_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 1.25, float -2.0)
ret float %res
}
@@ -43,7 +43,7 @@ define float @test_fmax_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -51,7 +51,7 @@ define float @test_fmax_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -59,7 +59,7 @@ define float @test_fmax_1_25_neg_2_nan_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_nan_f() {
; CHECK-NEXT: ret float 1.250000e+00
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 1.25, float -2.0)
ret float %res
}
@@ -67,7 +67,7 @@ define float @test_fmax_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -75,7 +75,7 @@ define float @test_fmax_1_25_neg_2_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_1_25_neg_2_xorsign_abs_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -87,7 +87,7 @@ define double @test_fmax_pos_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_zero_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0.0)
+ %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0.0)
ret double %res
}
@@ -95,7 +95,7 @@ define float @test_fmax_pos_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -103,7 +103,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -111,7 +111,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -119,7 +119,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -127,7 +127,7 @@ define float @test_fmax_pos_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -135,7 +135,7 @@ define float @test_fmax_pos_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -143,7 +143,7 @@ define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -151,7 +151,7 @@ define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_zero_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0.0)
ret float %res
}
@@ -163,7 +163,7 @@ define double @test_fmax_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_neg_subnorm_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
+ %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
}
@@ -171,7 +171,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -179,7 +179,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -187,7 +187,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -195,7 +195,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -203,7 +203,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -211,7 +211,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -219,7 +219,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -227,7 +227,7 @@ define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -239,7 +239,7 @@ define double @test_fmax_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmax_pos_subnorm_nan_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double 0x7fff444400000000)
+ %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
}
@@ -247,7 +247,7 @@ define float @test_fmax_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -255,7 +255,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -263,7 +263,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -271,7 +271,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -279,7 +279,7 @@ define float @test_fmax_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -287,7 +287,7 @@ define float @test_fmax_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -295,7 +295,7 @@ define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -303,7 +303,7 @@ define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -315,7 +315,7 @@ define double @test_fmax_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmax_subnorm_undef_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmax.f64(double 0x380FFFFFC0000000, double undef)
+ %res = call double @llvm.nvvm.fmax.d(double 0x380FFFFFC0000000, double undef)
ret double %res
}
@@ -323,7 +323,7 @@ define float @test_fmax_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -331,7 +331,7 @@ define float @test_fmax_subnorm_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -339,7 +339,7 @@ define float @test_fmax_subnorm_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -347,7 +347,7 @@ define float @test_fmax_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -355,7 +355,7 @@ define float @test_fmax_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -363,7 +363,7 @@ define float @test_fmax_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -371,7 +371,7 @@ define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -379,7 +379,7 @@ define float @test_fmax_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_subnorm_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -392,7 +392,7 @@ define double @test_fmax_nan_undef_d() {
; CHECK-LABEL: define double @test_fmax_nan_undef_d() {
; CHECK-NEXT: ret double 0x7FF4444400000000
;
- %res = call double @llvm.nvvm.fmax.f64(double 0x7ff4444400000000, double undef)
+ %res = call double @llvm.nvvm.fmax.d(double 0x7ff4444400000000, double undef)
ret double %res
}
@@ -400,7 +400,7 @@ define float @test_fmax_nan_undef_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -408,7 +408,7 @@ define float @test_fmax_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -416,7 +416,7 @@ define float @test_fmax_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -424,7 +424,7 @@ define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -432,7 +432,7 @@ define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32(float 0x7ffff4ff00000000, float undef)
+ %res = call float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
ret float %res
}
@@ -440,7 +440,7 @@ define float @test_fmax_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -448,7 +448,7 @@ define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -456,7 +456,7 @@ define float @test_fmax_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmax_nan_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmax.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmax.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -468,7 +468,7 @@ define double @test_fmin_1_25_neg_2_d() {
; CHECK-LABEL: define double @test_fmin_1_25_neg_2_d() {
; CHECK-NEXT: ret double -2.000000e+00
;
- %res = call double @llvm.nvvm.fmin.f64(double 1.25, double -2.0)
+ %res = call double @llvm.nvvm.fmin.d(double 1.25, double -2.0)
ret double %res
}
@@ -476,7 +476,7 @@ define float @test_fmin_1_25_neg_2_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.f(float 1.25, float -2.0)
ret float %res
}
@@ -484,7 +484,7 @@ define float @test_fmin_1_25_neg_2_ftz_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 1.25, float -2.0)
ret float %res
}
@@ -492,7 +492,7 @@ define float @test_fmin_1_25_neg_2_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_nan_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 1.25, float -2.0)
ret float %res
}
@@ -500,7 +500,7 @@ define float @test_fmin_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -508,7 +508,7 @@ define float @test_fmin_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -516,7 +516,7 @@ define float @test_fmin_1_25_neg_2_nan_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_nan_f() {
; CHECK-NEXT: ret float -2.000000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 1.25, float -2.0)
ret float %res
}
@@ -524,7 +524,7 @@ define float @test_fmin_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -532,7 +532,7 @@ define float @test_fmin_1_25_neg_2_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_1_25_neg_2_xorsign_abs_f() {
; CHECK-NEXT: ret float -1.250000e+00
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -544,7 +544,7 @@ define double @test_fmin_neg_subnorm_zero_d() {
; CHECK-LABEL: define double @test_fmin_neg_subnorm_zero_d() {
; CHECK-NEXT: ret double 0xB80FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.f64(double 0xB80FFFFFC0000000, double 0.0)
+ %res = call double @llvm.nvvm.fmin.d(double 0xB80FFFFFC0000000, double 0.0)
ret double %res
}
@@ -552,7 +552,7 @@ define float @test_fmin_neg_subnorm_zero_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -560,7 +560,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -568,7 +568,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_nan_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -576,7 +576,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -584,7 +584,7 @@ define float @test_fmin_neg_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -592,7 +592,7 @@ define float @test_fmin_neg_subnorm_zero_nan_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_nan_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -600,7 +600,7 @@ define float @test_fmin_neg_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -608,7 +608,7 @@ define float @test_fmin_neg_subnorm_zero_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_neg_subnorm_zero_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0xB80FFFFFC0000000, float 0.0)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0xB80FFFFFC0000000, float 0.0)
ret float %res
}
@@ -620,7 +620,7 @@ define double @test_fmin_pos_subnorm_neg_subnorm_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_neg_subnorm_d() {
; CHECK-NEXT: ret double 0xB80FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
+ %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0xB80FFFFFC0000000)
ret double %res
}
@@ -628,7 +628,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -636,7 +636,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -644,7 +644,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -652,7 +652,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -660,7 +660,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float -0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -668,7 +668,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -676,7 +676,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -684,7 +684,7 @@ define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_neg_subnorm_xorsign_abs_f() {
; CHECK-NEXT: ret float 0xB80FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0xB80FFFFFC0000000)
ret float %res
}
@@ -696,7 +696,7 @@ define double @test_fmin_pos_subnorm_nan_d() {
; CHECK-LABEL: define double @test_fmin_pos_subnorm_nan_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double 0x7fff444400000000)
+ %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double 0x7fff444400000000)
ret double %res
}
@@ -704,7 +704,7 @@ define float @test_fmin_pos_subnorm_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -712,7 +712,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -720,7 +720,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -728,7 +728,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -736,7 +736,7 @@ define float @test_fmin_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -744,7 +744,7 @@ define float @test_fmin_pos_subnorm_nan_nan_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -752,7 +752,7 @@ define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -760,7 +760,7 @@ define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_pos_subnorm_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float 0x7fff444400000000)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float 0x7fff444400000000)
ret float %res
}
@@ -772,7 +772,7 @@ define double @test_fmin_subnorm_undef_d() {
; CHECK-LABEL: define double @test_fmin_subnorm_undef_d() {
; CHECK-NEXT: ret double 0x380FFFFFC0000000
;
- %res = call double @llvm.nvvm.fmin.f64(double 0x380FFFFFC0000000, double undef)
+ %res = call double @llvm.nvvm.fmin.d(double 0x380FFFFFC0000000, double undef)
ret double %res
}
@@ -780,7 +780,7 @@ define float @test_fmin_subnorm_undef_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -788,7 +788,7 @@ define float @test_fmin_subnorm_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -796,7 +796,7 @@ define float @test_fmin_subnorm_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -804,7 +804,7 @@ define float @test_fmin_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -812,7 +812,7 @@ define float @test_fmin_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0.000000e+00
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -820,7 +820,7 @@ define float @test_fmin_subnorm_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -828,7 +828,7 @@ define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -836,7 +836,7 @@ define float @test_fmin_subnorm_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_subnorm_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x380FFFFFC0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x380FFFFFC0000000, float undef)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x380FFFFFC0000000, float undef)
ret float %res
}
@@ -849,7 +849,7 @@ define double @test_fmin_nan_undef_d() {
; CHECK-LABEL: define double @test_fmin_nan_undef_d() {
; CHECK-NEXT: ret double 0x7FF4444400000000
;
- %res = call double @llvm.nvvm.fmin.f64(double 0x7ff4444400000000, double undef)
+ %res = call double @llvm.nvvm.fmin.d(double 0x7ff4444400000000, double undef)
ret double %res
}
@@ -857,7 +857,7 @@ define float @test_fmin_nan_undef_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -865,7 +865,7 @@ define float @test_fmin_nan_undef_ftz_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -873,7 +873,7 @@ define float @test_fmin_nan_undef_ftz_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -881,7 +881,7 @@ define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -889,7 +889,7 @@ define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_ftz_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32(float 0x7ffff4ff00000000, float undef)
+ %res = call float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float 0x7ffff4ff00000000, float undef)
ret float %res
}
@@ -897,7 +897,7 @@ define float @test_fmin_nan_undef_nan_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -905,7 +905,7 @@ define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_nan_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.nan.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
@@ -913,6 +913,6 @@ define float @test_fmin_nan_undef_xorsign_abs_f() {
; CHECK-LABEL: define float @test_fmin_nan_undef_xorsign_abs_f() {
; CHECK-NEXT: ret float 0x7FFFFFFFE0000000
;
- %res = call float @llvm.nvvm.fmin.xorsign.abs.f32(float 0x7fff444400000000, float undef)
+ %res = call float @llvm.nvvm.fmin.xorsign.abs.f(float 0x7fff444400000000, float undef)
ret float %res
}
diff --git a/llvm/test/Transforms/InstSimplify/disable_folding.ll b/llvm/test/Transforms/InstSimplify/disable_folding.ll
index b014a20c0f4aa..521547f557915 100644
--- a/llvm/test/Transforms/InstSimplify/disable_folding.ll
+++ b/llvm/test/Transforms/InstSimplify/disable_folding.ll
@@ -13,7 +13,7 @@ define float @test_fmax_ftz_nan_xorsign_abs_f() {
; FOLDING_DISABLED-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.250000e+00, float -2.000000e+00)
; FOLDING_DISABLED-NEXT: ret float [[RES]]
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32(float 1.25, float -2.0)
+ %res = call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float 1.25, float -2.0)
ret float %res
}
@@ -36,7 +36,7 @@ define float @test_fmax_ftz_nan_f_strictfp() {
; CHECK-NEXT: [[RES:%.*]] = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.250000e+00, float -2.000000e+00) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret float [[RES]]
;
- %res = call float @llvm.nvvm.fmax.ftz.nan.f32(float 1.25, float -2.0) #1
+ %res = call float @llvm.nvvm.fmax.ftz.nan.f(float 1.25, float -2.0) #1
ret float %res
}
>From c04d6e56a52bbab1b2500ba17908c533681b7d47 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 02:45:15 -0700
Subject: [PATCH 05/13] [NVPTX] Fix bfloat FTZ check; fix [[fallthrough]]
placement
- Use isHalfTy() || isBFloatTy() for the IsHalfOrHalfVector predicate in
SimplifyNvvmIntrinsic so that bfloat and <2 x bfloat> use the generic
denormal-fp-math attribute rather than the f32-specific one when
deciding whether to simplify an ftz variant.
- Move [[fallthrough]] inside the compound statement of the intrinsic
cases in TargetLowering::getOperationAction(SDNode*, EVT).
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/include/llvm/CodeGen/TargetLowering.h | 2 +-
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 16 ++++++++--------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index ce8bca3383832..c5108fb4c6b8d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1319,8 +1319,8 @@ class LLVM_ABI TargetLoweringBase {
if (auto Action =
getIntrinsicAction(N->getConstantOperandVal(ConstIdx), VT))
return *Action;
- }
[[fallthrough]];
+ }
default:
return getOperationAction(N->getOpcode(), VT);
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index 901118fe4c9db..2308d19e43d87 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -215,27 +215,27 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
case Intrinsic::nvvm_fmax:
return {Intrinsic::maximumnum,
ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy()};
+ ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmax_ftz:
- return {Intrinsic::maximumnum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
+ return {Intrinsic::maximumnum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmax_nan:
return {Intrinsic::maximum,
ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy()};
+ ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmax_ftz_nan:
- return {Intrinsic::maximum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
+ return {Intrinsic::maximum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmin:
return {Intrinsic::minimumnum,
ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy()};
+ ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmin_ftz:
- return {Intrinsic::minimumnum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
+ return {Intrinsic::minimumnum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmin_nan:
return {Intrinsic::minimum,
ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy()};
+ ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_fmin_ftz_nan:
- return {Intrinsic::minimum, FTZ_MustBeOn, ScalarTy->isHalfTy()};
+ return {Intrinsic::minimum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
case Intrinsic::nvvm_sqrt_rn_d:
return {Intrinsic::sqrt, FTZ_Any};
case Intrinsic::nvvm_sqrt_f:
>From c9a4f5ce1b5c2e4c4fc483a38fdf00609c6a5dfc Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 02:57:53 -0700
Subject: [PATCH 06/13] [SelectionDAG] Fix GetOpVT operand mapping in
CanSplitVectorIntrinsic
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The descriptor-to-operand index mapping in the GetOpVT lambda was
off by one (WO_CHAIN) or two (W_CHAIN, VOID) because it didn't
account for the IntrinsicID constant operand (and chain_in operand
for W_CHAIN/VOID) that precede the actual intrinsic arguments in
the SDNode operand list.
WO_CHAIN operands: [IntrinsicID, arg0, arg1, ...] → +1
W_CHAIN operands: [chain_in, IntrinsicID, arg0, ...] → +3
VOID operands: [chain_in, IntrinsicID, arg0, ...] → +2
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index fe61ec0e66572..95325ce4af1ce 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -847,15 +847,18 @@ bool DAGTypeLegalizer::CanSplitVectorIntrinsic(const SDNode *N) {
auto GetOpVT = [&](unsigned I) -> EVT {
switch (N->getOpcode()) {
case ISD::INTRINSIC_WO_CHAIN:
+ // Operands: [IntrinsicID, arg0, arg1, ...]
return I < N->getNumValues()
? N->getValueType(I)
- : N->getOperand(I - N->getNumValues()).getValueType();
+ : N->getOperand(I - N->getNumValues() + 1).getValueType();
case ISD::INTRINSIC_W_CHAIN:
+ // Operands: [chain_in, IntrinsicID, arg0, arg1, ...]
return I < N->getNumValues() - 1
? N->getValueType(I)
- : N->getOperand(I - N->getNumValues() + 1).getValueType();
+ : N->getOperand(I - N->getNumValues() + 3).getValueType();
case ISD::INTRINSIC_VOID:
- return N->getOperand(I).getValueType();
+ // Operands: [chain_in, IntrinsicID, arg0, arg1, ...]
+ return N->getOperand(I + 2).getValueType();
default:
llvm_unreachable("Expected intrinsic opcode");
}
>From 29569a0138791a38b06d136789bc7e84368f2168 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 15:56:47 -0700
Subject: [PATCH 07/13] [NVPTX] Simplify fmin/fmax SimplifyAction and fix
SplitVecRes_INTRINSIC failure path
Extract repeated `ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()` and
`ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff` into local variables in the
SimplifyAction lambda in NVPTXTargetTransformInfo.cpp.
Initialize Lo/Hi to SDValue() before returning on the failure path in
SplitVecRes_INTRINSIC to avoid leaving output parameters uninitialized.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
.../SelectionDAG/LegalizeVectorTypes.cpp | 4 ++-
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 27 ++++++++-----------
2 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 95325ce4af1ce..9c0f22bde76ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3769,8 +3769,10 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_INTERLEAVE(SDNode *N) {
void DAGTypeLegalizer::SplitVecRes_INTRINSIC(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- if (!CanSplitVectorIntrinsic(N))
+ if (!CanSplitVectorIntrinsic(N)) {
+ Lo = Hi = SDValue();
return;
+ }
SmallVector<SDValue> Operands1, Operands2;
for (auto [I, Op] : enumerate(N->ops())) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index 2308d19e43d87..80fcb490a1f0f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -180,6 +180,9 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
// IntrinsicInstr with target-generic LLVM IR.
const SimplifyAction Action = [II, RetTy]() -> SimplifyAction {
Type *ScalarTy = RetTy->getScalarType();
+ const bool IsHalfOrBFloat = ScalarTy->isHalfTy() || ScalarTy->isBFloatTy();
+ const FtzRequirementTy NonF32FtzReq =
+ ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff;
switch (II->getIntrinsicID()) {
// NVVM intrinsics that map directly to LLVM intrinsics.
case Intrinsic::nvvm_ceil_d:
@@ -213,29 +216,21 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC,
case Intrinsic::nvvm_fma_rn_bf16x2:
return {Intrinsic::fma, FTZ_MustBeOff, true};
case Intrinsic::nvvm_fmax:
- return {Intrinsic::maximumnum,
- ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::maximumnum, NonF32FtzReq, IsHalfOrBFloat};
case Intrinsic::nvvm_fmax_ftz:
- return {Intrinsic::maximumnum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::maximumnum, FTZ_MustBeOn, IsHalfOrBFloat};
case Intrinsic::nvvm_fmax_nan:
- return {Intrinsic::maximum,
- ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::maximum, NonF32FtzReq, IsHalfOrBFloat};
case Intrinsic::nvvm_fmax_ftz_nan:
- return {Intrinsic::maximum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::maximum, FTZ_MustBeOn, IsHalfOrBFloat};
case Intrinsic::nvvm_fmin:
- return {Intrinsic::minimumnum,
- ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::minimumnum, NonF32FtzReq, IsHalfOrBFloat};
case Intrinsic::nvvm_fmin_ftz:
- return {Intrinsic::minimumnum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::minimumnum, FTZ_MustBeOn, IsHalfOrBFloat};
case Intrinsic::nvvm_fmin_nan:
- return {Intrinsic::minimum,
- ScalarTy->isDoubleTy() ? FTZ_Any : FTZ_MustBeOff,
- ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::minimum, NonF32FtzReq, IsHalfOrBFloat};
case Intrinsic::nvvm_fmin_ftz_nan:
- return {Intrinsic::minimum, FTZ_MustBeOn, ScalarTy->isHalfTy() || ScalarTy->isBFloatTy()};
+ return {Intrinsic::minimum, FTZ_MustBeOn, IsHalfOrBFloat};
case Intrinsic::nvvm_sqrt_rn_d:
return {Intrinsic::sqrt, FTZ_Any};
case Intrinsic::nvvm_sqrt_f:
>From eace38c8d897216882a0481412147038c893cdb8 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Wed, 29 Apr 2026 16:05:45 -0700
Subject: [PATCH 08/13] [NFC] Fix clang-format in AutoUpgrade.cpp
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/lib/IR/AutoUpgrade.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index a4e31d261c4cf..c52ebe58acc7e 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -1710,8 +1710,8 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn,
Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs)
.Default(Intrinsic::not_intrinsic);
if (IID != Intrinsic::not_intrinsic) {
- NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), IID,
- {NewTy});
+ NewFn =
+ Intrinsic::getOrInsertDeclaration(F->getParent(), IID, {NewTy});
return true;
}
}
>From eebb69f24969b549533081879155d772f9c2b802 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Fri, 1 May 2026 01:21:53 -0700
Subject: [PATCH 09/13] [NVPTX] Fix float NaN canonicalization for
nvvm_fmax/fmin with undef operand
In ConstantFoldIntrinsicCall2, nvvm_fmax/nvvm_fmin were in the undef-return
group that returns the non-undef operand as-is. This was wrong for float NaN
inputs: PTX hardware canonicalizes f32 NaNs to 0x7FFFFFFF, but doubles are
returned unchanged.
Fix by falling through to the existing NaN-canonicalization group when the
non-undef operand is a float NaN. The fallthrough path already handles this
correctly for all the modifier variants (ftz, nan, xorsign_abs).
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
llvm/lib/Analysis/ConstantFolding.cpp | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index a5561373b166a..2d3a7028bcc73 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -3433,11 +3433,15 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
case Intrinsic::minimumnum:
case Intrinsic::nvvm_fmax:
case Intrinsic::nvvm_fmin:
- // If one argument is undef, return the other argument.
- if (IsOp0Undef)
- return Operands[1];
- if (IsOp1Undef)
- return Operands[0];
+ // If one argument is undef, return the other argument — unless it is a
+ // float NaN, in which case fall through to canonicalize it. Double NaNs
+ // are returned as-is; PTX only canonicalizes f32 NaNs.
+ if (IsOp0Undef || IsOp1Undef) {
+ Constant *Other = Operands[IsOp0Undef ? 1 : 0];
+ auto *Op = dyn_cast<ConstantFP>(Other);
+ if (!Op || !Op->isNaN() || Ty->isDoubleTy())
+ return Other;
+ }
[[fallthrough]];
case Intrinsic::nvvm_fmax_ftz:
>From 695f499251d34f667a8f413474626e8868befdae Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Fri, 1 May 2026 09:18:00 -0700
Subject: [PATCH 10/13] [NVPTX][clang] Update fmax/fmin f16/f16x2 builtins to
use generic overloaded intrinsic
The type-specific nvvm_fmax_f16, nvvm_fmax_f16x2, nvvm_fmin_f16, nvvm_fmin_f16x2
intrinsic IDs (and their ftz/nan/xorsign_abs modifier variants) were replaced by the
generic overloaded nvvm_fmax/nvvm_fmin family. Update the 32 builtin codegen cases in
NVPTX.cpp to use the new IDs with an explicit type argument, and add a
MakeHalfType overload that accepts a type for use with overloaded intrinsics.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp | 133 +++++++++++++--------
1 file changed, 85 insertions(+), 48 deletions(-)
diff --git a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
index e2d494103a5c9..d26609404197e 100644
--- a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
@@ -415,6 +415,13 @@ static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF);
}
+static Value *MakeHalfType(unsigned IntrinsicID, llvm::Type *Ty,
+ unsigned BuiltinID, const CallExpr *E,
+ CodeGenFunction &CGF) {
+ return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID, {Ty}), BuiltinID, E,
+ CGF);
+}
+
static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
const CallExpr *E, CodeGenFunction &CGF) {
return CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(IntrinsicID, {Ty}),
@@ -1014,87 +1021,117 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
llvm::FixedVectorType::get(Builder.getBFloatTy(), 2), E,
*this);
case NVPTX::BI__nvvm_fmax_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getHalfTy(), BuiltinID, E,
+ *this);
case NVPTX::BI__nvvm_fmax_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_nan_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_nan_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getHalfTy(), BuiltinID, E,
+ *this);
case NVPTX::BI__nvvm_fmin_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_nan_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_nan_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ Builder.getHalfTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
- E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
- return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs, Builder.getHalfTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
- return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
- *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fabs_f:
case NVPTX::BI__nvvm_abs_bf16:
case NVPTX::BI__nvvm_abs_bf16x2:
>From 30279f13a1e1e9906caa0664a7429d68c0bbaa2e Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Fri, 1 May 2026 12:02:23 -0700
Subject: [PATCH 11/13] [Clang][NVPTX] Update codegen test CHECK patterns for
renamed fmin/fmax intrinsics
The generic overloaded nvvm_fmin/fmax intrinsics use LLVM type-mangled
suffixes (.v2f16, .v2bf16) instead of the old type-specific suffixes
(.f16x2, .bf16x2).
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
.../builtins-nvptx-native-half-type-native.c | 34 +++++++++----------
.../CodeGen/builtins-nvptx-native-half-type.c | 32 ++++++++---------
clang/test/CodeGen/builtins-nvptx.c | 26 +++++++-------
3 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
index 60a35f4fe0c37..4ea410c902303 100644
--- a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
+++ b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
@@ -8,7 +8,7 @@
typedef __fp16 __fp16v2 __attribute__((ext_vector_type(2)));
// CHECK: call half @llvm.nvvm.ex2.approx.f16(half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.v2f16(<2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.f16x2(<2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.ftz.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call <2 x half> @llvm.nvvm.fma.rn.relu.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}}, <2 x half> {{.*}})
@@ -24,34 +24,34 @@ typedef __fp16 __fp16v2 __attribute__((ext_vector_type(2)));
// CHECK: call half @llvm.nvvm.fmin.ftz.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmin.nan.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmin.ftz.nan.f16(half {{.*}}, half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.nan.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.nan.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.nan.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.nan.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fmin.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmin.ftz.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmin.nan.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16(half {{.*}}, half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fmax.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.ftz.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.nan.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.ftz.nan.f16(half {{.*}}, half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.nan.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.nan.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.nan.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.nan.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fmax.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.ftz.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.nan.xorsign.abs.f16(half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16(half {{.*}}, half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.v2f16(<2 x half> {{.*}}, <2 x half> {{.*}})
// CHECK: load half, ptr addrspace(1) {{.*}}, align 2, !invariant.load
// CHECK: load <2 x half>, ptr addrspace(1) {{.*}}, align 4, !invariant.load
// CHECK: call half @llvm.nvvm.ldu.global.f.f16.p0(ptr {{.*}}, i32 2)
diff --git a/clang/test/CodeGen/builtins-nvptx-native-half-type.c b/clang/test/CodeGen/builtins-nvptx-native-half-type.c
index 1f16c7e54b85d..365cd746c3a74 100644
--- a/clang/test/CodeGen/builtins-nvptx-native-half-type.c
+++ b/clang/test/CodeGen/builtins-nvptx-native-half-type.c
@@ -58,13 +58,13 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmin_nan_f16(0.1f16, 0.1f16);
// CHECK_PTX70_SM80: call half @llvm.nvvm.fmin.ftz.nan.f16
__nvvm_fmin_ftz_nan_f16(0.1f16, 0.1f16);
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.v2f16
__nvvm_fmin_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.ftz.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.ftz.v2f16
__nvvm_fmin_ftz_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.nan.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.nan.v2f16
__nvvm_fmin_nan_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.ftz.nan.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmin.ftz.nan.v2f16
__nvvm_fmin_ftz_nan_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
// CHECK_PTX70_SM80: call half @llvm.nvvm.fmax.f16
@@ -75,13 +75,13 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmax_nan_f16(0.1f16, 0.1f16);
// CHECK_PTX70_SM80: call half @llvm.nvvm.fmax.ftz.nan.f16
__nvvm_fmax_ftz_nan_f16(0.1f16, 0.1f16);
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.v2f16
__nvvm_fmax_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.ftz.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.ftz.v2f16
__nvvm_fmax_ftz_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.nan.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.nan.v2f16
__nvvm_fmax_nan_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.ftz.nan.f16x2
+ // CHECK_PTX70_SM80: call <2 x half> @llvm.nvvm.fmax.ftz.nan.v2f16
__nvvm_fmax_ftz_nan_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
#endif
// CHECK: ret void
@@ -144,13 +144,13 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmin_nan_xorsign_abs_f16(0.1f16, 0.1f16);
// CHECK_PTX72_SM86: call half @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16
__nvvm_fmin_ftz_nan_xorsign_abs_f16(0.1f16, 0.1f16);
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.xorsign.abs.v2f16
__nvvm_fmin_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.v2f16
__nvvm_fmin_ftz_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.v2f16
__nvvm_fmin_nan_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.v2f16
__nvvm_fmin_ftz_nan_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
// CHECK_PTX72_SM86: call half @llvm.nvvm.fmax.xorsign.abs.f16
@@ -161,13 +161,13 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmax_nan_xorsign_abs_f16(0.1f16, 0.1f16);
// CHECK_PTX72_SM86: call half @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16
__nvvm_fmax_ftz_nan_xorsign_abs_f16(0.1f16, 0.1f16);
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.xorsign.abs.v2f16
__nvvm_fmax_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.v2f16
__nvvm_fmax_ftz_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.v2f16
__nvvm_fmax_nan_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
- // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2
+ // CHECK_PTX72_SM86: call <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.v2f16
__nvvm_fmax_ftz_nan_xorsign_abs_f16x2({0.1f16, 0.7f16}, {0.1f16, 0.7f16});
#endif
// CHECK: ret void
diff --git a/clang/test/CodeGen/builtins-nvptx.c b/clang/test/CodeGen/builtins-nvptx.c
index f1b41ba557426..395804d678ce5 100644
--- a/clang/test/CodeGen/builtins-nvptx.c
+++ b/clang/test/CodeGen/builtins-nvptx.c
@@ -1418,7 +1418,7 @@ __device__ void nvvm_abs_neg_bf16_bf16x2_sm80() {
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fabs.bf16(bfloat 0xR3DCD)
__nvvm_abs_bf16(BF16);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fabs.v2bf16(<2 x bfloat> splat (bfloat 0xR3DCD))
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fabs.bf16x2(<2 x bfloat> splat (bfloat 0xR3DCD))
__nvvm_abs_bf16x2(BF16X2);
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.neg.bf16(bfloat 0xR3DCD)
@@ -1446,13 +1446,13 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmin_nan_bf16(BF16, NANBF16);
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fmin.ftz.nan.bf16
__nvvm_fmin_ftz_nan_bf16(BF16, NANBF16);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.v2bf16
__nvvm_fmin_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.ftz.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.ftz.v2bf16
__nvvm_fmin_ftz_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.nan.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.nan.v2bf16
__nvvm_fmin_nan_bf16x2(BF16X2, NANBF16X2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.ftz.nan.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.ftz.nan.v2bf16
__nvvm_fmin_ftz_nan_bf16x2(BF16X2, NANBF16X2);
// CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f
__nvvm_fmax_nan_f(0.1f, 0.11f);
@@ -1471,13 +1471,13 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmax_nan_bf16(BF16, NANBF16);
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fmax.ftz.nan.bf16
__nvvm_fmax_ftz_nan_bf16(BF16, NANBF16);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.v2bf16
__nvvm_fmax_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.ftz.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.ftz.v2bf16
__nvvm_fmax_ftz_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.nan.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.nan.v2bf16
__nvvm_fmax_nan_bf16x2(NANBF16X2, BF16X2);
- // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.ftz.nan.bf16x2
+ // CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.ftz.nan.v2bf16
__nvvm_fmax_ftz_nan_bf16x2(NANBF16X2, BF16X2);
// CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f
__nvvm_fmax_nan_f(0.1f, (float)NAN32);
@@ -1511,9 +1511,9 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmin_xorsign_abs_bf16(BF16, BF16_2);
// CHECK_PTX72_SM86: call bfloat @llvm.nvvm.fmin.nan.xorsign.abs.bf16
__nvvm_fmin_nan_xorsign_abs_bf16(BF16, NANBF16);
- // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmin.xorsign.abs.bf16x2
+ // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmin.xorsign.abs.v2bf16
__nvvm_fmin_xorsign_abs_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2
+ // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmin.nan.xorsign.abs.v2bf16
__nvvm_fmin_nan_xorsign_abs_bf16x2(BF16X2, NANBF16X2);
// CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.xorsign.abs.f
__nvvm_fmin_xorsign_abs_f(-0.1f, 0.1f);
@@ -1528,9 +1528,9 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmax_xorsign_abs_bf16(BF16, BF16_2);
// CHECK_PTX72_SM86: call bfloat @llvm.nvvm.fmax.nan.xorsign.abs.bf16
__nvvm_fmax_nan_xorsign_abs_bf16(BF16, NANBF16);
- // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmax.xorsign.abs.bf16x2
+ // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmax.xorsign.abs.v2bf16
__nvvm_fmax_xorsign_abs_bf16x2(BF16X2, BF16X2_2);
- // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2
+ // CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmax.nan.xorsign.abs.v2bf16
__nvvm_fmax_nan_xorsign_abs_bf16x2(BF16X2, NANBF16X2);
// CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.xorsign.abs.f
__nvvm_fmax_xorsign_abs_f(-0.1f, 0.1f);
>From 614d69554eb17e0159195722439e23f0d18fd7f9 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Fri, 1 May 2026 22:39:19 -0700
Subject: [PATCH 12/13] [NVPTX][clang] Add codegen for float/double fmin/fmax
builtins; fix ex2.approx CHECK
The float/double fmin/fmax builtins (__nvvm_fmin_f, __nvvm_fmax_f,
__nvvm_fmin_d, __nvvm_fmax_d and their ftz/nan/xorsign_abs modifier
variants) previously relied on the Clang auto-mechanism resolving
type-specific intrinsic names. After those intrinsics were merged into
the generic overloaded nvvm_fmin/nvvm_fmax family, the auto-mechanism
no longer works (it can't instantiate overloaded intrinsics without a
type). Add 18 explicit switch cases in EmitNVPTXBuiltinExpr using the
existing MakeHalfType(IntrinsicID, Type, ...) overload.
Update all float/double CHECK patterns in builtins-nvptx.c to use the
new LLVM type-mangled suffixes (.f32, .f64). Also fix a one-line
regression in builtins-nvptx-native-half-type-native.c where the
ex2.approx.v2f16 CHECK was incorrectly reverted to ex2.approx.f16x2.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp | 54 +++++++++++++++++++
.../builtins-nvptx-native-half-type-native.c | 2 +-
clang/test/CodeGen/builtins-nvptx.c | 40 +++++++-------
3 files changed, 75 insertions(+), 21 deletions(-)
diff --git a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
index d26609404197e..88295ff805023 100644
--- a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
@@ -1132,6 +1132,60 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs,
llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_nan_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_d:
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getDoubleTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_nan_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs, Builder.getFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs,
+ Builder.getFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_d:
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getDoubleTy(),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_fabs_f:
case NVPTX::BI__nvvm_abs_bf16:
case NVPTX::BI__nvvm_abs_bf16x2:
diff --git a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
index 4ea410c902303..10327f585d269 100644
--- a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
+++ b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
@@ -8,7 +8,7 @@
typedef __fp16 __fp16v2 __attribute__((ext_vector_type(2)));
// CHECK: call half @llvm.nvvm.ex2.approx.f16(half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.f16x2(<2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.v2f16(<2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.ftz.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call <2 x half> @llvm.nvvm.fma.rn.relu.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}}, <2 x half> {{.*}})
diff --git a/clang/test/CodeGen/builtins-nvptx.c b/clang/test/CodeGen/builtins-nvptx.c
index 395804d678ce5..d4a8c821bf7f6 100644
--- a/clang/test/CodeGen/builtins-nvptx.c
+++ b/clang/test/CodeGen/builtins-nvptx.c
@@ -237,9 +237,9 @@ __device__ void exit() {
// The idea is not to test all intrinsics, just that Clang is recognizing the
// builtins defined in BuiltinsNVPTX.td
__device__ void nvvm_math(float f1, float f2, double d1, double d2) {
-// CHECK: call float @llvm.nvvm.fmax.f
+// CHECK: call float @llvm.nvvm.fmax.f32
float t1 = __nvvm_fmax_f(f1, f2);
-// CHECK: call float @llvm.nvvm.fmin.f
+// CHECK: call float @llvm.nvvm.fmin.f32
float t2 = __nvvm_fmin_f(f1, f2);
// CHECK: call float @llvm.nvvm.sqrt.rn.f
float t3 = __nvvm_sqrt_rn_f(f1);
@@ -248,9 +248,9 @@ __device__ void nvvm_math(float f1, float f2, double d1, double d2) {
// CHECK: call float @llvm.nvvm.add.rn.f
float t5 = __nvvm_add_rn_f(f1, f2);
-// CHECK: call double @llvm.nvvm.fmax.d
+// CHECK: call double @llvm.nvvm.fmax.f64
double td1 = __nvvm_fmax_d(d1, d2);
-// CHECK: call double @llvm.nvvm.fmin.d
+// CHECK: call double @llvm.nvvm.fmin.f64
double td2 = __nvvm_fmin_d(d1, d2);
// CHECK: call double @llvm.nvvm.sqrt.rn.d
double td3 = __nvvm_sqrt_rn_d(d1);
@@ -1433,9 +1433,9 @@ __device__ void nvvm_abs_neg_bf16_bf16x2_sm80() {
__device__ void nvvm_min_max_sm80() {
#if __CUDA_ARCH__ >= 800
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmin.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmin.nan.f32
__nvvm_fmin_nan_f(0.1f, (float)NAN32);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmin.ftz.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmin.ftz.nan.f32
__nvvm_fmin_ftz_nan_f(0.1f, (float)NAN32);
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fmin.bf16
@@ -1454,14 +1454,14 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmin_nan_bf16x2(BF16X2, NANBF16X2);
// CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmin.ftz.nan.v2bf16
__nvvm_fmin_ftz_nan_bf16x2(BF16X2, NANBF16X2);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f32
__nvvm_fmax_nan_f(0.1f, 0.11f);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f32
__nvvm_fmax_ftz_nan_f(0.1f, (float)NAN32);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f32
__nvvm_fmax_nan_f(0.1f, (float)NAN32);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f32
__nvvm_fmax_ftz_nan_f(0.1f, (float)NAN32);
// CHECK_PTX70_SM80: call bfloat @llvm.nvvm.fmax.bf16
__nvvm_fmax_bf16(BF16, BF16_2);
@@ -1479,9 +1479,9 @@ __device__ void nvvm_min_max_sm80() {
__nvvm_fmax_nan_bf16x2(NANBF16X2, BF16X2);
// CHECK_PTX70_SM80: call <2 x bfloat> @llvm.nvvm.fmax.ftz.nan.v2bf16
__nvvm_fmax_ftz_nan_bf16x2(NANBF16X2, BF16X2);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.nan.f32
__nvvm_fmax_nan_f(0.1f, (float)NAN32);
- // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f
+ // CHECK_PTX70_SM80: call float @llvm.nvvm.fmax.ftz.nan.f32
__nvvm_fmax_ftz_nan_f(0.1f, (float)NAN32);
#endif
@@ -1515,13 +1515,13 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmin_xorsign_abs_bf16x2(BF16X2, BF16X2_2);
// CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmin.nan.xorsign.abs.v2bf16
__nvvm_fmin_nan_xorsign_abs_bf16x2(BF16X2, NANBF16X2);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.xorsign.abs.f32
__nvvm_fmin_xorsign_abs_f(-0.1f, 0.1f);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.ftz.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.ftz.xorsign.abs.f32
__nvvm_fmin_ftz_xorsign_abs_f(-0.1f, 0.1f);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.nan.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.nan.xorsign.abs.f32
__nvvm_fmin_nan_xorsign_abs_f(-0.1f, (float)NAN32);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f32
__nvvm_fmin_ftz_nan_xorsign_abs_f(-0.1f, (float)NAN32);
// CHECK_PTX72_SM86: call bfloat @llvm.nvvm.fmax.xorsign.abs.bf16
@@ -1532,13 +1532,13 @@ __device__ void nvvm_min_max_sm86() {
__nvvm_fmax_xorsign_abs_bf16x2(BF16X2, BF16X2_2);
// CHECK_PTX72_SM86: call <2 x bfloat> @llvm.nvvm.fmax.nan.xorsign.abs.v2bf16
__nvvm_fmax_nan_xorsign_abs_bf16x2(BF16X2, NANBF16X2);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.xorsign.abs.f32
__nvvm_fmax_xorsign_abs_f(-0.1f, 0.1f);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.ftz.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.ftz.xorsign.abs.f32
__nvvm_fmax_ftz_xorsign_abs_f(-0.1f, 0.1f);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.nan.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.nan.xorsign.abs.f32
__nvvm_fmax_nan_xorsign_abs_f(-0.1f, (float)NAN32);
- // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f
+ // CHECK_PTX72_SM86: call float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f32
__nvvm_fmax_ftz_nan_xorsign_abs_f(-0.1f, (float)NAN32);
#endif
// CHECK: ret void
>From eb2892addb02df9bbac0b8d62ef7ac73664ca067 Mon Sep 17 00:00:00 2001
From: Princeton Ferro <pferro at nvidia.com>
Date: Sat, 2 May 2026 22:54:39 -0700
Subject: [PATCH 13/13] [NVPTX][clang] Add codegen for bf16/bf16x2 fmin/fmax
builtins; fix clang-format
The bf16 and bf16x2 fmin/fmax builtins (__nvvm_fmin_bf16, __nvvm_fmax_bf16,
__nvvm_fmin_bf16x2, __nvvm_fmax_bf16x2, and their ftz/nan/xorsign_abs variants)
had the same missing-codegen problem as the float/double variants fixed in the
previous commit. Add 24 explicit switch cases using MakeHalfType with
Builder.getBFloatTy() and FixedVectorType::get(getBFloatTy(), 2).
Also reformat 4 earlier MakeHalfType call sites to satisfy clang-format
(BI__nvvm_fmax_f, BI__nvvm_fmax_d, BI__nvvm_fmin_f, BI__nvvm_fmin_d).
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
---
clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp | 98 ++++++++++++++++++++--
1 file changed, 91 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
index 88295ff805023..03a476426d9c8 100644
--- a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
@@ -1133,8 +1133,8 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
llvm::FixedVectorType::get(Builder.getHalfTy(), 2),
BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_f:
- return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getFloatTy(),
- BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getFloatTy(), BuiltinID,
+ E, *this);
case NVPTX::BI__nvvm_fmax_ftz_f:
return MakeHalfType(Intrinsic::nvvm_fmax_ftz, Builder.getFloatTy(),
BuiltinID, E, *this);
@@ -1157,11 +1157,11 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs,
Builder.getFloatTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmax_d:
- return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getDoubleTy(),
- BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getDoubleTy(), BuiltinID,
+ E, *this);
case NVPTX::BI__nvvm_fmin_f:
- return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getFloatTy(),
- BuiltinID, E, *this);
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getFloatTy(), BuiltinID,
+ E, *this);
case NVPTX::BI__nvvm_fmin_ftz_f:
return MakeHalfType(Intrinsic::nvvm_fmin_ftz, Builder.getFloatTy(),
BuiltinID, E, *this);
@@ -1184,7 +1184,91 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs,
Builder.getFloatTy(), BuiltinID, E, *this);
case NVPTX::BI__nvvm_fmin_d:
- return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getDoubleTy(),
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getDoubleTy(), BuiltinID,
+ E, *this);
+ case NVPTX::BI__nvvm_fmax_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax, Builder.getBFloatTy(), BuiltinID,
+ E, *this);
+ case NVPTX::BI__nvvm_fmax_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_nan_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_ftz_nan_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax_ftz_nan,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_xorsign_abs_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs,
+ Builder.getBFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_xorsign_abs_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs,
+ Builder.getBFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmax_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin, Builder.getBFloatTy(), BuiltinID,
+ E, *this);
+ case NVPTX::BI__nvvm_fmin_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_nan_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan, Builder.getBFloatTy(),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_ftz_nan_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin_ftz_nan,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_xorsign_abs_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs,
+ Builder.getBFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_xorsign_abs_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
+ BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_bf16:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ Builder.getBFloatTy(), BuiltinID, E, *this);
+ case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_bf16x2:
+ return MakeHalfType(Intrinsic::nvvm_fmin_nan_xorsign_abs,
+ llvm::FixedVectorType::get(Builder.getBFloatTy(), 2),
BuiltinID, E, *this);
case NVPTX::BI__nvvm_fabs_f:
case NVPTX::BI__nvvm_abs_bf16:
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