[clang] [CIR][AArch64] Upstream addition-across-vector (incl. widening) NEON builtins (PR #193396)
Vicky Nguyen via cfe-commits
cfe-commits at lists.llvm.org
Thu Apr 30 21:38:40 PDT 2026
================
@@ -4302,206 +4255,338 @@ float64_t test_vminnmvq_f64(float64x2_t a) {
}
//===----------------------------------------------------------------------===//
-// 2.1.3.2.2 Vector rounding shift right
-// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right
+// 2.1.9.1 Addition across vector
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition-across-vector
//===----------------------------------------------------------------------===//
-// ALL-LABEL: @test_vrshr_n_s8(
-int8x8_t test_vrshr_n_s8(int8x8_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// LLVM-LABEL: @test_vaddv_s8(
+// CIR-LABEL: @vaddv_s8(
+int8_t test_vaddv_s8(int8x8_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<8 x !s8i>) -> !s8i
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
-// LLVM: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
-// LLVM: ret <8 x i8> [[VRSHR_N]]
- return vrshr_n_s8(a, 3);
+// LLVM: [[VADDV_I:%.*]] = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> [[A]])
+// LLVM-NEXT: ret i8 [[VADDV_I]]
+ return vaddv_s8(a);
+}
+
+// LLVM-LABEL: @test_vaddvq_s8(
+// CIR-LABEL: @vaddvq_s8(
+int8_t test_vaddvq_s8(int8x16_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<16 x !s8i>) -> !s8i
+
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[A]])
+// LLVM-NEXT: ret i8 [[VADDVQ_I]]
+ return vaddvq_s8(a);
}
-// ALL-LABEL: @test_vrshr_n_s16(
-int16x4_t test_vrshr_n_s16(int16x4_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_s16(
+// CIR-LABEL: @vaddv_s16(
+int16_t test_vaddv_s16(int16x4_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<4 x !s16i>) -> !s16i
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
-// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// LLVM: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// LLVM: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
-// LLVM: ret <4 x i16> [[VRSHR_N1]]
- return vrshr_n_s16(a, 3);
+// LLVM: [[VADDV_I:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[A]])
+// LLVM-NEXT: ret i16 [[VADDV_I]]
+ return vaddv_s16(a);
}
-// ALL-LABEL: @test_vrshr_n_s32(
-int32x2_t test_vrshr_n_s32(int32x2_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_s16(
+// CIR-LABEL: @vaddvq_s16(
+int16_t test_vaddvq_s16(int16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<8 x !s16i>) -> !s16i
-// CHECK-SAME: <2 x i32> {{.*}} [[A:%.*]])
-// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
-// CHECK: ret <2 x i32> [[VRSHR_N1]]
- return vrshr_n_s32(a, 3);
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[A]])
+// LLVM-NEXT: ret i16 [[VADDVQ_I]]
+ return vaddvq_s16(a);
}
-// ALL-LABEL: @test_vrshr_n_s64(
-int64x1_t test_vrshr_n_s64(int64x1_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_s32(
+// CIR-LABEL: @vaddv_s32(
+int32_t test_vaddv_s32(int32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<2 x !s32i>) -> !s32i
-// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
-// CHECK: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
-// CHECK: ret <16 x i8> [[VRSHR_N]]
- return vrshr_n_s64(a, 1);
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VADDV_I:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[A]])
+// LLVM-NEXT: ret i32 [[VADDV_I]]
+ return vaddv_s32(a);
}
-// ALL-LABEL: @test_vrshr_n_u8(
-uint8x8_t test_vrshr_n_u8(uint8x8_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_s32(
+// CIR-LABEL: @vaddvq_s32(
+int32_t test_vaddvq_s32(int32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<4 x !s32i>) -> !s32i
-// CHECK-SAME: <8 x i8> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]
- return vrshr_n_u8(a, 3);
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[A]])
+// LLVM-NEXT: ret i32 [[VADDVQ_I]]
+ return vaddvq_s32(a);
}
-// ALL-LABEL: @test_vrshr_n_u16(
-uint16x4_t test_vrshr_n_u16(uint16x4_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_s64(
+// CIR-LABEL: @vaddvq_s64(
+int64_t test_vaddvq_s64(int64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<2 x !s64i>) -> !s64i
-// CHECK-SAME: <4 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]
- return vrshr_n_u16(a, 3);
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[A]])
+// LLVM-NEXT: ret i64 [[VADDVQ_I]]
+ return vaddvq_s64(a);
}
-// ALL-LABEL: @test_vrshr_n_u32(
-uint32x2_t test_vrshr_n_u32(uint32x2_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_u8(
+// CIR-LABEL: @vaddv_u8(
+uint8_t test_vaddv_u8(uint8x8_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<8 x !u8i>) -> !u8i
-// CHECK-SAME: <2 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <2 x i32> [[VRSHR_N1]]
- return vrshr_n_u32(a, 3);
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VADDV_I:%.*]] = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> [[A]])
+// LLVM-NEXT: ret i8 [[VADDV_I]]
+ return vaddv_u8(a);
}
-// ALL-LABEL: @test_vrshr_n_u64(
-uint64x1_t test_vrshr_n_u64(uint64x1_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_u8(
+// CIR-LABEL: @vaddvq_u8(
+uint8_t test_vaddvq_u8(uint8x16_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<16 x !u8i>) -> !u8i
-// CHECK-SAME: <1 x i64> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1))
-// CHECK-NEXT: ret <1 x i64> [[VRSHR_N1]]
- return vrshr_n_u64(a, 1);
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> [[A]])
+// LLVM-NEXT: ret i8 [[VADDVQ_I]]
+ return vaddvq_u8(a);
}
-// ALL-LABEL: @test_vrshrq_n_s8(
-int8x16_t test_vrshrq_n_s8(int8x16_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_u16(
+// CIR-LABEL: @vaddv_u16(
+uint16_t test_vaddv_u16(uint16x4_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<4 x !u16i>) -> !u16i
-// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
- return vrshrq_n_s8(a, 3);
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VADDV_I:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[A]])
+// LLVM-NEXT: ret i16 [[VADDV_I]]
+ return vaddv_u16(a);
}
-// ALL-LABEL: @test_vrshrq_n_s16(
-int16x8_t test_vrshrq_n_s16(int16x8_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_u16(
+// CIR-LABEL: @vaddvq_u16(
+uint16_t test_vaddvq_u16(uint16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<8 x !u16i>) -> !u16i
-// CHECK-SAME: <8 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
- return vrshrq_n_s16(a, 3);
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[A]])
+// LLVM-NEXT: ret i16 [[VADDVQ_I]]
+ return vaddvq_u16(a);
}
-// ALL-LABEL: @test_vrshrq_n_s32(
-int32x4_t test_vrshrq_n_s32(int32x4_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_u32(
+// CIR-LABEL: @vaddv_u32(
+uint32_t test_vaddv_u32(uint32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<2 x !u32i>) -> !u32i
-// CHECK-SAME: <4 x i32> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
- return vrshrq_n_s32(a, 3);
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VADDV_I:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[A]])
+// LLVM-NEXT: ret i32 [[VADDV_I]]
+ return vaddv_u32(a);
}
-// ALL-LABEL: @test_vrshrq_n_s64(
-int64x2_t test_vrshrq_n_s64(int64x2_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_u32(
+// CIR-LABEL: @vaddvq_u32(
+uint32_t test_vaddvq_u32(uint32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<4 x !u32i>) -> !u32i
-// CHECK-SAME: <2 x i64> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
-// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
- return vrshrq_n_s64(a, 3);
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[A]])
+// LLVM-NEXT: ret i32 [[VADDVQ_I]]
+ return vaddvq_u32(a);
}
-// ALL-LABEL: @test_vrshrq_n_u8(
-uint8x16_t test_vrshrq_n_u8(uint8x16_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_u64(
+// CIR-LABEL: @vaddvq_u64(
+uint64_t test_vaddvq_u64(uint64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "vector.reduce.add" %{{.*}} : (!cir.vector<2 x !u64i>) -> !u64i
-// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
- return vrshrq_n_u8(a, 3);
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_I:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[A]])
+// LLVM-NEXT: ret i64 [[VADDVQ_I]]
+ return vaddvq_u64(a);
}
-// ALL-LABEL: @test_vrshrq_n_u16(
-uint16x8_t test_vrshrq_n_u16(uint16x8_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddv_f32(
+// CIR-LABEL: @vaddv_f32(
+float32_t test_vaddv_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.faddv" %{{.*}} : (!cir.vector<2 x !cir.float>) -> !cir.float
-// CHECK-SAME: <8 x i16> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
- return vrshrq_n_u16(a, 3);
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VADDV_F32_I:%.*]] = call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> [[A]])
+// LLVM-NEXT: ret float [[VADDV_F32_I]]
+ return vaddv_f32(a);
}
-// ALL-LABEL: @test_vrshrq_n_u32(
-uint32x4_t test_vrshrq_n_u32(uint32x4_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_f32(
+// CIR-LABEL: @vaddvq_f32(
+float32_t test_vaddvq_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.faddv" %{{.*}} : (!cir.vector<4 x !cir.float>) -> !cir.float
-// CHECK-SAME: <4 x i32> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
- return vrshrq_n_u32(a, 3);
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> [[A]])
+// LLVM-NEXT: ret float [[VADDVQ_F32_I]]
+ return vaddvq_f32(a);
}
-// ALL-LABEL: @test_vrshrq_n_u64(
-uint64x2_t test_vrshrq_n_u64(uint64x2_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+// LLVM-LABEL: @test_vaddvq_f64(
+// CIR-LABEL: @vaddvq_f64(
+float64_t test_vaddvq_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.faddv" %{{.*}} : (!cir.vector<2 x !cir.double>) -> !cir.double
-// CHECK-SAME: <2 x i64> {{.*}} [[A:%.*]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
-// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
- return vrshrq_n_u64(a, 3);
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[VADDVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> [[A]])
+// LLVM-NEXT: ret double [[VADDVQ_F64_I]]
+ return vaddvq_f64(a);
}
-// vrshrd_n_* (scalar 64-bit)
-// ALL-LABEL: @test_vrshrd_n_s64(
-int64_t test_vrshrd_n_s64(int64_t a) {
-// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+//===----------------------------------------------------------------------===//
+// 2.1.9.2 Addition across vector widening
----------------
iamvickynguyen wrote:
Thank you for catching this! I edited it.
https://github.com/llvm/llvm-project/pull/193396
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