[clang] [CIR][AArch64] Implement vqshrn_n NEON builtin (PR #195085)
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Thu Apr 30 06:48:05 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
Author: Jingyan5
<details>
<summary>Changes</summary>
Implement CIR support for vqshrn_n NEON intrinsic variants (s16, s32,
s64, u16, u32, u64). Lowers __builtin_neon_vqshrn_n_v to
aarch64.neon.sqshrn or aarch64.neon.uqshrn via emitNeonCall, with
signed/unsigned dispatch using the usgn flag.
Tests verify both the traditional LLVM codegen path and the
CIR-to-CIR path with full intrinsic type signatures.
Part of #<!-- -->185382
---
Full diff: https://github.com/llvm/llvm-project/pull/195085.diff
3 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+29-2)
- (added) clang/test/CodeGen/AArch64/neon/vqshrn.c (+73)
- (added) clang/test/CodeGen/AArch64/neon/vqshrun.c (+28)
``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index ace8a5737f4bd..9557e955fdd25 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2540,13 +2540,40 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vmaxnmq_v:
intrName = "aarch64.neon.fmaxnm";
return emitNeonCall(cgm, builder, {ty, ty}, ops, intrName, ty, loc);
+ case NEON::BI__builtin_neon_vqshrun_n_v:
+ intrName = "aarch64.neon.sqshrun";
+ return emitNeonCall(cgm, builder, {ty, ty}, ops, intrName, ty, loc);
+ case NEON::BI__builtin_neon_vqshrn_n_v: {
+ mlir::Type inputTy;
+
+ switch (type.getEltType()) {
+ case NeonTypeFlags::Int8:
+ inputTy = getNeonType(
+ this, NeonTypeFlags(NeonTypeFlags::Int16, false, true), loc);
+ break;
+ case NeonTypeFlags::Int16:
+ inputTy = getNeonType(
+ this, NeonTypeFlags(NeonTypeFlags::Int32, false, true), loc);
+ break;
+ case NeonTypeFlags::Int32:
+ inputTy = getNeonType(
+ this, NeonTypeFlags(NeonTypeFlags::Int64, false, true), loc);
+ break;
+ default:
+ llvm_unreachable("unexpected vqshrn element type");
+ }
+
+ auto shiftTy = ops[1].getType();
+ ops[0] = builder.createBitcast(loc, ops[0], inputTy);
+
+ intrName = usgn ? "aarch64.neon.uqshrn" : "aarch64.neon.sqshrn";
+ return emitNeonCall(cgm, builder, {inputTy, shiftTy}, ops, intrName, ty, loc);
+ }
case NEON::BI__builtin_neon_vmaxnmh_f16:
case NEON::BI__builtin_neon_vrecpss_f32:
case NEON::BI__builtin_neon_vrecpsd_f64:
case NEON::BI__builtin_neon_vrecpsh_f16:
- case NEON::BI__builtin_neon_vqshrun_n_v:
case NEON::BI__builtin_neon_vqrshrun_n_v:
- case NEON::BI__builtin_neon_vqshrn_n_v:
case NEON::BI__builtin_neon_vrshrn_n_v:
case NEON::BI__builtin_neon_vqrshrn_n_v:
case NEON::BI__builtin_neon_vrndah_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/vqshrn.c b/clang/test/CodeGen/AArch64/neon/vqshrn.c
new file mode 100644
index 0000000000000..62f8f569b9d03
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/vqshrn.c
@@ -0,0 +1,73 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa,simplifycfg | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa,simplifycfg | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+
+#include <arm_neon.h>
+
+// LLVM-LABEL: @test_vqshrn_n_s16(
+// CIR-LABEL: @test_vqshrn_n_s16(
+int8x8_t test_vqshrn_n_s16(int16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrn" {{.*}} : (!cir.vector<8 x !s16i>, !s32i) -> !cir.vector<8 x !s8i>
+
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> {{.*}}, i32 3)
+// LLVM-NEXT: ret <8 x i8> [[R]]
+ return vqshrn_n_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vqshrn_n_s32(
+// CIR-LABEL: @test_vqshrn_n_s32(
+int16x4_t test_vqshrn_n_s32(int32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrn" {{.*}} : (!cir.vector<4 x !s32i>, !s32i) -> !cir.vector<4 x !s16i>
+
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> {{.*}}, i32 9)
+// LLVM-NEXT: ret <4 x i16> [[R]]
+ return vqshrn_n_s32(a, 9);
+}
+
+// LLVM-LABEL: @test_vqshrn_n_s64(
+// CIR-LABEL: @test_vqshrn_n_s64(
+int32x2_t test_vqshrn_n_s64(int64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrn" {{.*}} : (!cir.vector<2 x !s64i>, !s32i) -> !cir.vector<2 x !s32i>
+
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> {{.*}}, i32 19)
+// LLVM-NEXT: ret <2 x i32> [[R]]
+ return vqshrn_n_s64(a, 19);
+}
+
+// LLVM-LABEL: @test_vqshrn_n_u16(
+// CIR-LABEL: @test_vqshrn_n_u16(
+uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshrn" {{.*}} : (!cir.vector<8 x !s16i>, !s32i) -> !cir.vector<8 x !u8i>
+
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> {{.*}}, i32 3)
+// LLVM-NEXT: ret <8 x i8> [[R]]
+ return vqshrn_n_u16(a, 3);
+}
+
+// LLVM-LABEL: @test_vqshrn_n_u32(
+// CIR-LABEL: @test_vqshrn_n_u32(
+uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshrn" {{.*}} : (!cir.vector<4 x !s32i>, !s32i) -> !cir.vector<4 x !u16i>
+
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> {{.*}}, i32 9)
+// LLVM-NEXT: ret <4 x i16> [[R]]
+ return vqshrn_n_u32(a, 9);
+}
+
+// LLVM-LABEL: @test_vqshrn_n_u64(
+// CIR-LABEL: @test_vqshrn_n_u64(
+uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshrn" {{.*}} : (!cir.vector<2 x !s64i>, !s32i) -> !cir.vector<2 x !u32i>
+
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) {{.*}} {
+// LLVM: [[R:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> {{.*}}, i32 19)
+// LLVM-NEXT: ret <2 x i32> [[R]]
+ return vqshrn_n_u64(a, 19);
+}
diff --git a/clang/test/CodeGen/AArch64/neon/vqshrun.c b/clang/test/CodeGen/AArch64/neon/vqshrun.c
new file mode 100644
index 0000000000000..016377b845183
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/vqshrun.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fclangir -emit-cir -o - %s | FileCheck %s --check-prefix=CIR
+
+#include <arm_neon.h>
+
+// LLVM-LABEL: @test_vqshrun_n_s16(
+// CIR-LABEL: @test_vqshrun_n_s16(
+uint8x8_t test_vqshrun_n_s16(int16x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrun"
+ // LLVM: call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8
+ return vqshrun_n_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vqshrun_n_s32(
+// CIR-LABEL: @test_vqshrun_n_s32(
+uint16x4_t test_vqshrun_n_s32(int32x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrun"
+ // LLVM: call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16
+ return vqshrun_n_s32(a, 9);
+}
+
+// LLVM-LABEL: @test_vqshrun_n_s64(
+// CIR-LABEL: @test_vqshrun_n_s64(
+uint32x2_t test_vqshrun_n_s64(int64x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshrun"
+ // LLVM: call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32
+ return vqshrun_n_s64(a, 19);
+}
\ No newline at end of file
``````````
</details>
https://github.com/llvm/llvm-project/pull/195085
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