[clang] [llvm] [RISCV] Add partial support for -fzero-call-used-regs (PR #194883)

[Craig Topper via cfe-commits]

================
@@ -3935,6 +3939,22 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
   return It;
 }
 
+void RISCVInstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator Iter,
+                                        DebugLoc &DL,
+                                        bool AllowSideEffects) const {
+
+  const MachineFunction &MF = *MBB.getParent();
+  const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
+  const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
+
+  if (TRI.isGeneralPurposeRegister(MF, Reg)) {
+    BuildMI(MBB, Iter, DL, get(RISCV::PseudoLI), Reg).addImm(0);
----------------
topperc wrote:

PseudoLI is tagged as `isAsmParserOnly` it should not be used in CodeGen. Use ADDI X0, 0

https://github.com/llvm/llvm-project/pull/194883