[clang] [llvm] [RISCV] Add partial support for -fzero-call-used-regs (PR #194883)

[Craig Topper via cfe-commits]

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@@ -1433,6 +1433,27 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   emitSiFiveCLICStackSwap(MF, MBB, MBBI, DL);
 }
 
+void RISCVFrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
+                                              MachineBasicBlock &MBB) const {
+  // Insertion point.
+  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
+
+  // Fake a debug loc.
+  DebugLoc DL;
+  if (MBBI != MBB.end())
+    DL = MBBI->getDebugLoc();
+
+  const MachineFunction &MF = *MBB.getParent();
+  const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
+  const RISCVRegisterInfo &TRI = STI.getTargetABI();
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topperc wrote:

This line makes no sense to me. Is this passing a RISCVABI::ABI to the RISCVRegisterInfo constructior which expects a HwMode?

https://github.com/llvm/llvm-project/pull/194883