[clang] [CIR] max-across-vector (vmaxv_*) intrinsics (PR #194401)
Kartik Ohlan via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 29 09:26:43 PDT 2026
https://github.com/Ko496-glitch updated https://github.com/llvm/llvm-project/pull/194401
>From e2ae68c34080f4ef2f5375c37d9514d93353282f Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Mon, 27 Apr 2026 11:26:28 -0400
Subject: [PATCH 1/8] Added vmax_v and removed the existing test cases
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 15 +++++++
clang/test/CodeGen/AArch64/neon-intrinsics.c | 40 ++++++++---------
clang/test/CodeGen/AArch64/neon/intrinsics.c | 44 +++++++++++++++++++
3 files changed, 79 insertions(+), 20 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 294e87168b0e5..bd621e06efa83 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -317,6 +317,21 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
case NEON::BI__builtin_neon_vcvtd_n_f64_u64:
case NEON::BI__builtin_neon_vcvtd_n_s64_f64:
case NEON::BI__builtin_neon_vcvtd_n_u64_f64:
+ case NEON::BI__builtin_neon_vmaxv_s8:
+ case NEON::BI__builtin_neon_vmaxvq_s8:
+ case NEON::BI__builtin_neon_vmaxv_s16:
+ case NEON::BI__builtin_neon_vmaxvq_s16:
+ case NEON::BI__builtin_neon_vmaxv_s32:
+ case NEON::BI__builtin_neon_vmaxvq_s32:
+ case NEON::BI__builtin_neon_vmaxv_u8:
+ case NEON::BI__builtin_neon_vmaxvq_u8:
+ case NEON::BI__builtin_neon_vmaxv_u16:
+ case NEON::BI__builtin_neon_vmaxvq_u16:
+ case NEON::BI__builtin_neon_vmaxv_u32:
+ case NEON::BI__builtin_neon_vmaxvq_u32:
+ case NEON::BI__builtin_neon_vmaxv_f32:
+ case NEON::BI__builtin_neon_vmaxvq_f32:
+ case NEON::BI__builtin_neon_vmaxvq_f64:
return emitNeonCall(cgf.cgm, cgf.getBuilder(),
{cgf.convertType(expr->getArg(0)->getType())}, ops,
llvmIntrName, cgf.convertType(expr->getType()), loc);
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 920a0236bb433..eee77c8c75afa 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -20337,24 +20337,24 @@ float64_t test_vaddvq_f64(float64x2_t a) {
return vaddvq_f64(a);
}
-// CHECK-LABEL: define dso_local float @test_vmaxv_f32(
+// CHECK-LABEL: define dso_local float @test_vminv_f32(
// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMAXV_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> [[A]])
-// CHECK-NEXT: ret float [[VMAXV_F32_I]]
+// CHECK-NEXT: [[VMINV_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> [[A]])
+// CHECK-NEXT: ret float [[VMINV_F32_I]]
//
-float32_t test_vmaxv_f32(float32x2_t a) {
- return vmaxv_f32(a);
+float32_t test_vminv_f32(float32x2_t a) {
+ return vminv_f32(a);
}
-// CHECK-LABEL: define dso_local double @test_vmaxvq_f64(
+// CHECK-LABEL: define dso_local double @test_vminvq_f64(
// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMAXVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[A]])
-// CHECK-NEXT: ret double [[VMAXVQ_F64_I]]
+// CHECK-NEXT: [[VMINVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> [[A]])
+// CHECK-NEXT: ret double [[VMINVQ_F64_I]]
//
-float64_t test_vmaxvq_f64(float64x2_t a) {
- return vmaxvq_f64(a);
+float64_t test_vminvq_f64(float64x2_t a) {
+ return vminvq_f64(a);
}
// CHECK-LABEL: define dso_local double @test_vmaxnmvq_f64(
@@ -20925,24 +20925,24 @@ float64x1_t test_vrsqrts_f64(float64x1_t a, float64x1_t b) {
return vrsqrts_f64(a, b);
}
-// CHECK-LABEL: define dso_local i32 @test_vmaxv_s32(
+// CHECK-LABEL: define dso_local i32 @test_vminv_s32(
// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMAXV_S32_I]]
+// CHECK-NEXT: [[VMINV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> [[A]])
+// CHECK-NEXT: ret i32 [[VMINV_S32_I]]
//
-int32_t test_vmaxv_s32(int32x2_t a) {
- return vmaxv_s32(a);
+int32_t test_vminv_s32(int32x2_t a) {
+ return vminv_s32(a);
}
-// CHECK-LABEL: define dso_local i32 @test_vmaxv_u32(
+// CHECK-LABEL: define dso_local i32 @test_vminv_u32(
// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMAXV_U32_I]]
+// CHECK-NEXT: [[VMINV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> [[A]])
+// CHECK-NEXT: ret i32 [[VMINV_U32_I]]
//
-uint32_t test_vmaxv_u32(uint32x2_t a) {
- return vmaxv_u32(a);
+uint32_t test_vminv_u32(uint32x2_t a) {
+ return vminv_u32(a);
}
// CHECK-LABEL: define dso_local i32 @test_vaddv_s32(
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index bf14d1abc9d8e..dda734a13fd6a 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -24,6 +24,50 @@
#include <arm_neon.h>
+//===------------------------------------------------------===//
+// 2.1.1.13 Maximum across vector
+//===------------------------------------------------------===//
+
+//ALL-LABEL: @test_vmaxv_f64(
+float64_t test_vmaxvq_f64(float64x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
+
+// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[A]])
+// LLVM: ret double [[VMAXVQ_F64_I]]
+ return vmaxvq_f64(a);
+}
+
+//ALL-LABEL: @test_vmaxv_f32(
+float32_t test_vmaxv_f32(float32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
+
+// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> [[A]])
+// LLVM: ret float [[VMAXV_F32_I]]
+ return vmaxv_f32(a);
+}
+
+//ALL-LABEL: @test_vmaxv_u32(
+uint32_t test_vmaxv_u32(uint32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_U32_I]]
+ return vmaxv_u32(a);
+}
+
+//ALL-LABEL: @test_vmaxv_s32(
+int32_t test_vmaxv_s32(int32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_S32_I]]
+ return vmaxv_s32(a);
+}
+
// LLVM-LABEL: @test_vnegd_s64
// CIR-LABEL: @vnegd_s64
int64_t test_vnegd_s64(int64_t a) {
>From 2412f1ad8fd62699e1a9be17ec0820523c4c7b91 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Mon, 27 Apr 2026 12:16:22 -0400
Subject: [PATCH 2/8] resolved the conflicts
---
clang/test/CodeGen/AArch64/neon-intrinsics.c | 40 --------------------
1 file changed, 40 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index eee77c8c75afa..767b31eead9b4 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -20337,26 +20337,6 @@ float64_t test_vaddvq_f64(float64x2_t a) {
return vaddvq_f64(a);
}
-// CHECK-LABEL: define dso_local float @test_vminv_f32(
-// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMINV_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> [[A]])
-// CHECK-NEXT: ret float [[VMINV_F32_I]]
-//
-float32_t test_vminv_f32(float32x2_t a) {
- return vminv_f32(a);
-}
-
-// CHECK-LABEL: define dso_local double @test_vminvq_f64(
-// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMINVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> [[A]])
-// CHECK-NEXT: ret double [[VMINVQ_F64_I]]
-//
-float64_t test_vminvq_f64(float64x2_t a) {
- return vminvq_f64(a);
-}
-
// CHECK-LABEL: define dso_local double @test_vmaxnmvq_f64(
// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -20925,26 +20905,6 @@ float64x1_t test_vrsqrts_f64(float64x1_t a, float64x1_t b) {
return vrsqrts_f64(a, b);
}
-// CHECK-LABEL: define dso_local i32 @test_vminv_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMINV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMINV_S32_I]]
-//
-int32_t test_vminv_s32(int32x2_t a) {
- return vminv_s32(a);
-}
-
-// CHECK-LABEL: define dso_local i32 @test_vminv_u32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VMINV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMINV_U32_I]]
-//
-uint32_t test_vminv_u32(uint32x2_t a) {
- return vminv_u32(a);
-}
-
// CHECK-LABEL: define dso_local i32 @test_vaddv_s32(
// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
>From a9c1e45621fc206074000178b5ea577d33013d50 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Mon, 27 Apr 2026 15:32:31 -0400
Subject: [PATCH 3/8] Update intrinsics.c
Fixed the missing }
---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 4268e5b699462..5a6c4b84d5315 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -66,6 +66,8 @@ int32_t test_vmaxv_s32(int32x2_t a) {
// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
// LLVM: ret i32 [[VMAXV_S32_I]]
return vmaxv_s32(a);
+}
+
// 2.1.3.2 Vector Saturating Shift Left
//
// TODO: Implement the remaining intrinsics from this group.
>From d7d4f9647e634fb121ee28ebb83c7a7095b56084 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Mon, 27 Apr 2026 19:11:00 -0400
Subject: [PATCH 4/8] Added the test cases
---
clang/test/CodeGen/AArch64/neon-across.c | 110 -----------------
clang/test/CodeGen/AArch64/neon/intrinsics.c | 122 ++++++++++++++++++-
2 files changed, 118 insertions(+), 114 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon-across.c b/clang/test/CodeGen/AArch64/neon-across.c
index 7a76173c54882..a12897ef6fadb 100644
--- a/clang/test/CodeGen/AArch64/neon-across.c
+++ b/clang/test/CodeGen/AArch64/neon-across.c
@@ -110,106 +110,6 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) {
return vaddlvq_u32(a);
}
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s8
-// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]])
-// CHECK-NEXT: ret i8 [[VMAXV_S8_I]]
-//
-int8_t test_vmaxv_s8(int8x8_t a) {
- return vmaxv_s8(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s16
-// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]])
-// CHECK-NEXT: ret i16 [[VMAXV_S16_I]]
-//
-int16_t test_vmaxv_s16(int16x4_t a) {
- return vmaxv_s16(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u8
-// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]])
-// CHECK-NEXT: ret i8 [[VMAXV_U8_I]]
-//
-uint8_t test_vmaxv_u8(uint8x8_t a) {
- return vmaxv_u8(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u16
-// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]])
-// CHECK-NEXT: ret i16 [[VMAXV_U16_I]]
-//
-uint16_t test_vmaxv_u16(uint16x4_t a) {
- return vmaxv_u16(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s8
-// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]])
-// CHECK-NEXT: ret i8 [[VMAXVQ_S8_I]]
-//
-int8_t test_vmaxvq_s8(int8x16_t a) {
- return vmaxvq_s8(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s16
-// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]])
-// CHECK-NEXT: ret i16 [[VMAXVQ_S16_I]]
-//
-int16_t test_vmaxvq_s16(int16x8_t a) {
- return vmaxvq_s16(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s32
-// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMAXVQ_S32_I]]
-//
-int32_t test_vmaxvq_s32(int32x4_t a) {
- return vmaxvq_s32(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u8
-// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]])
-// CHECK-NEXT: ret i8 [[VMAXVQ_U8_I]]
-//
-uint8_t test_vmaxvq_u8(uint8x16_t a) {
- return vmaxvq_u8(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u16
-// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]])
-// CHECK-NEXT: ret i16 [[VMAXVQ_U16_I]]
-//
-uint16_t test_vmaxvq_u16(uint16x8_t a) {
- return vmaxvq_u16(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u32
-// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]])
-// CHECK-NEXT: ret i32 [[VMAXVQ_U32_I]]
-//
-uint32_t test_vmaxvq_u32(uint32x4_t a) {
- return vmaxvq_u32(a);
-}
-
// CHECK-LABEL: define {{[^@]+}}@test_vaddv_s8
// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
@@ -310,16 +210,6 @@ uint32_t test_vaddvq_u32(uint32x4_t a) {
return vaddvq_u32(a);
}
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f32
-// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])
-// CHECK-NEXT: ret float [[VMAXVQ_F32_I]]
-//
-float32_t test_vmaxvq_f32(float32x4_t a) {
- return vmaxvq_f32(a);
-}
-
// CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f32
// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 5a6c4b84d5315..2caeabcb373f1 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -28,7 +28,118 @@
// 2.1.1.13 Maximum across vector
//===------------------------------------------------------===//
-//ALL-LABEL: @test_vmaxv_f64(
+// LLVM-LABEL: @test_vmaxv_s8(
+// CIR-LABEL: @test_vmaxv_s8(
+int8_t test_vmaxv_s8(int8x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_s8({{%.*}}) : (!cir.vector<8 x !s8i> {{.*}}) -> !s8i
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]])
+// LLVM: ret i8 [[VMAXV_S8_I]]
+ return vmaxv_s8(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s8(
+// CIR-LABEL: @test_vmaxvq_s8(
+int8_t test_vmaxvq_s8(int8x16_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s8({{%.*}}) : (!cir.vector<16 x !s8i> {{.*}}) -> !s8i
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]])
+// LLVM: ret i8 [[VMAXVQ_S8_I]]
+ return vmaxvq_s8(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_s16(
+// CIR-LABEL: @test_vmaxv_s16(
+int16_t test_vmaxv_s16(int16x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_s16({{%.*}}) : (!cir.vector<4 x !s16i> {{.*}}) -> !s16i
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]])
+// LLVM: ret i16 [[VMAXV_S16_I]]
+ return vmaxv_s16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s16(
+// CIR-LABEL: @test_vmaxvq_s16(
+int16_t test_vmaxvq_s16(int16x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s16({{%.*}}) : (!cir.vector<8 x !s16i> {{.*}}) -> !s16i
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]])
+// LLVM: ret i16 [[VMAXVQ_S16_I]]
+ return vmaxvq_s16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s32(
+// CIR-LABEL: @test_vmaxvq_s32(
+int32_t test_vmaxvq_s32(int32x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s32({{%.*}}) : (!cir.vector<4 x !s32i> {{.*}}) -> !s32i
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]])
+// LLVM: ret i32 [[VMAXVQ_S32_I]]
+ return vmaxvq_s32(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_u8(
+// CIR-LABEL: @test_vmaxv_u8(
+uint8_t test_vmaxv_u8(uint8x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_u8({{%.*}}) : (!cir.vector<8 x !u8i> {{.*}}) -> !u8i
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]])
+// LLVM: ret i8 [[VMAXV_U8_I]]
+ return vmaxv_u8(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u8(
+// CIR-LABEL: @test_vmaxvq_u8(
+uint8_t test_vmaxvq_u8(uint8x16_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u8({{%.*}}) : (!cir.vector<16 x !u8i> {{.*}}) -> !u8i
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]])
+// LLVM: ret i8 [[VMAXVQ_U8_I]]
+ return vmaxvq_u8(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_u16(
+// CIR-LABEL: @test_vmaxv_u16(
+uint16_t test_vmaxv_u16(uint16x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_u16({{%.*}}) : (!cir.vector<4 x !u16i> {{.*}}) -> !u16i
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]])
+// LLVM: ret i16 [[VMAXV_U16_I]]
+ return vmaxv_u16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u16(
+// CIR-LABEL: @test_vmaxvq_u16(
+uint16_t test_vmaxvq_u16(uint16x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u16({{%.*}}) : (!cir.vector<8 x !u16i> {{.*}}) -> !u16i
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]])
+// LLVM: ret i16 [[VMAXVQ_U16_I]]
+ return vmaxvq_u16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u32(
+// CIR-LABEL: @test_vmaxvq_u32(
+uint32_t test_vmaxvq_u32(uint32x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u32({{%.*}}) : (!cir.vector<4 x !u32i> {{.*}}) -> !u32i
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]])
+// LLVM: ret i32 [[VMAXVQ_U32_I]]
+ return vmaxvq_u32(a);
+}
+
+//LLVM-LABEL: @test_vmaxvq_f64(
+//CIR-LABEL : @test_vmaxvq_f64(
float64_t test_vmaxvq_f64(float64x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
@@ -38,7 +149,8 @@ float64_t test_vmaxvq_f64(float64x2_t a) {
return vmaxvq_f64(a);
}
-//ALL-LABEL: @test_vmaxv_f32(
+//LLVM-LABEL: @test_vmaxv_f32
+//CIR-LABEL : @test_vmaxv_f32
float32_t test_vmaxv_f32(float32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
@@ -48,7 +160,8 @@ float32_t test_vmaxv_f32(float32x2_t a) {
return vmaxv_f32(a);
}
-//ALL-LABEL: @test_vmaxv_u32(
+//LLVM-LABEL: @test_vmaxv_u32(
+//CIR-LABEL : @test_vmaxv_u32(
uint32_t test_vmaxv_u32(uint32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
@@ -58,7 +171,8 @@ uint32_t test_vmaxv_u32(uint32x2_t a) {
return vmaxv_u32(a);
}
-//ALL-LABEL: @test_vmaxv_s32(
+//LLVM-LABEL: @test_vmaxv_s32
+//CIR-LABEL : @test_vmaxv_s32
int32_t test_vmaxv_s32(int32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
>From 187d48e74e20565be08ccf4cf692c87eded34434 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Tue, 28 Apr 2026 09:41:42 -0400
Subject: [PATCH 5/8] Added the vmaxvq_f32 test case (15/15)
---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 39 +++++++++++++-------
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 2caeabcb373f1..37ac6472fbe77 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -28,8 +28,19 @@
// 2.1.1.13 Maximum across vector
//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vmaxvq_f32(
+// CIR-LABEL: @vmaxvq_f32(
+float32_t test_vmaxvq_f32(float32x4_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
+
+// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])
+// LLVM: ret float [[VMAXVQ_F32_I]]
+ return vmaxvq_f32(a);
+}
+
// LLVM-LABEL: @test_vmaxv_s8(
-// CIR-LABEL: @test_vmaxv_s8(
+// CIR-LABEL: @vmaxv_s8(
int8_t test_vmaxv_s8(int8x8_t a) {
// CIR: {{%.*}} = cir.call @vmaxv_s8({{%.*}}) : (!cir.vector<8 x !s8i> {{.*}}) -> !s8i
@@ -40,7 +51,7 @@ int8_t test_vmaxv_s8(int8x8_t a) {
}
// LLVM-LABEL: @test_vmaxvq_s8(
-// CIR-LABEL: @test_vmaxvq_s8(
+// CIR-LABEL: @vmaxvq_s8(
int8_t test_vmaxvq_s8(int8x16_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_s8({{%.*}}) : (!cir.vector<16 x !s8i> {{.*}}) -> !s8i
@@ -51,7 +62,7 @@ int8_t test_vmaxvq_s8(int8x16_t a) {
}
// LLVM-LABEL: @test_vmaxv_s16(
-// CIR-LABEL: @test_vmaxv_s16(
+// CIR-LABEL: @vmaxv_s16(
int16_t test_vmaxv_s16(int16x4_t a) {
// CIR: {{%.*}} = cir.call @vmaxv_s16({{%.*}}) : (!cir.vector<4 x !s16i> {{.*}}) -> !s16i
@@ -62,7 +73,7 @@ int16_t test_vmaxv_s16(int16x4_t a) {
}
// LLVM-LABEL: @test_vmaxvq_s16(
-// CIR-LABEL: @test_vmaxvq_s16(
+// CIR-LABEL: @vmaxvq_s16(
int16_t test_vmaxvq_s16(int16x8_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_s16({{%.*}}) : (!cir.vector<8 x !s16i> {{.*}}) -> !s16i
@@ -73,7 +84,7 @@ int16_t test_vmaxvq_s16(int16x8_t a) {
}
// LLVM-LABEL: @test_vmaxvq_s32(
-// CIR-LABEL: @test_vmaxvq_s32(
+// CIR-LABEL: @vmaxvq_s32(
int32_t test_vmaxvq_s32(int32x4_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_s32({{%.*}}) : (!cir.vector<4 x !s32i> {{.*}}) -> !s32i
@@ -84,7 +95,7 @@ int32_t test_vmaxvq_s32(int32x4_t a) {
}
// LLVM-LABEL: @test_vmaxv_u8(
-// CIR-LABEL: @test_vmaxv_u8(
+// CIR-LABEL: @vmaxv_u8(
uint8_t test_vmaxv_u8(uint8x8_t a) {
// CIR: {{%.*}} = cir.call @vmaxv_u8({{%.*}}) : (!cir.vector<8 x !u8i> {{.*}}) -> !u8i
@@ -95,7 +106,7 @@ uint8_t test_vmaxv_u8(uint8x8_t a) {
}
// LLVM-LABEL: @test_vmaxvq_u8(
-// CIR-LABEL: @test_vmaxvq_u8(
+// CIR-LABEL: @vmaxvq_u8(
uint8_t test_vmaxvq_u8(uint8x16_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_u8({{%.*}}) : (!cir.vector<16 x !u8i> {{.*}}) -> !u8i
@@ -106,7 +117,7 @@ uint8_t test_vmaxvq_u8(uint8x16_t a) {
}
// LLVM-LABEL: @test_vmaxv_u16(
-// CIR-LABEL: @test_vmaxv_u16(
+// CIR-LABEL: @vmaxv_u16(
uint16_t test_vmaxv_u16(uint16x4_t a) {
// CIR: {{%.*}} = cir.call @vmaxv_u16({{%.*}}) : (!cir.vector<4 x !u16i> {{.*}}) -> !u16i
@@ -117,7 +128,7 @@ uint16_t test_vmaxv_u16(uint16x4_t a) {
}
// LLVM-LABEL: @test_vmaxvq_u16(
-// CIR-LABEL: @test_vmaxvq_u16(
+// CIR-LABEL: @vmaxvq_u16(
uint16_t test_vmaxvq_u16(uint16x8_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_u16({{%.*}}) : (!cir.vector<8 x !u16i> {{.*}}) -> !u16i
@@ -128,7 +139,7 @@ uint16_t test_vmaxvq_u16(uint16x8_t a) {
}
// LLVM-LABEL: @test_vmaxvq_u32(
-// CIR-LABEL: @test_vmaxvq_u32(
+// CIR-LABEL: @vmaxvq_u32(
uint32_t test_vmaxvq_u32(uint32x4_t a) {
// CIR: {{%.*}} = cir.call @vmaxvq_u32({{%.*}}) : (!cir.vector<4 x !u32i> {{.*}}) -> !u32i
@@ -139,7 +150,7 @@ uint32_t test_vmaxvq_u32(uint32x4_t a) {
}
//LLVM-LABEL: @test_vmaxvq_f64(
-//CIR-LABEL : @test_vmaxvq_f64(
+//CIR-LABEL : @vmaxvq_f64(
float64_t test_vmaxvq_f64(float64x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
@@ -150,7 +161,7 @@ float64_t test_vmaxvq_f64(float64x2_t a) {
}
//LLVM-LABEL: @test_vmaxv_f32
-//CIR-LABEL : @test_vmaxv_f32
+//CIR-LABEL : @vmaxv_f32
float32_t test_vmaxv_f32(float32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
@@ -161,7 +172,7 @@ float32_t test_vmaxv_f32(float32x2_t a) {
}
//LLVM-LABEL: @test_vmaxv_u32(
-//CIR-LABEL : @test_vmaxv_u32(
+//CIR-LABEL : @vmaxv_u32(
uint32_t test_vmaxv_u32(uint32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
@@ -172,7 +183,7 @@ uint32_t test_vmaxv_u32(uint32x2_t a) {
}
//LLVM-LABEL: @test_vmaxv_s32
-//CIR-LABEL : @test_vmaxv_s32
+//CIR-LABEL : @vmaxv_s32
int32_t test_vmaxv_s32(int32x2_t a) {
// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
>From cba7fb4ae3285c3df92284576a6d98cd956f1194 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Tue, 28 Apr 2026 11:11:00 -0400
Subject: [PATCH 6/8] Reordered test cases
---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 79 ++++++++++----------
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 37ac6472fbe77..95685912123fd 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -28,17 +28,6 @@
// 2.1.1.13 Maximum across vector
//===------------------------------------------------------===//
-// LLVM-LABEL: @test_vmaxvq_f32(
-// CIR-LABEL: @vmaxvq_f32(
-float32_t test_vmaxvq_f32(float32x4_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
-
-// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])
-// LLVM: ret float [[VMAXVQ_F32_I]]
- return vmaxvq_f32(a);
-}
-
// LLVM-LABEL: @test_vmaxv_s8(
// CIR-LABEL: @vmaxv_s8(
int8_t test_vmaxv_s8(int8x8_t a) {
@@ -83,6 +72,17 @@ int16_t test_vmaxvq_s16(int16x8_t a) {
return vmaxvq_s16(a);
}
+//LLVM-LABEL: @test_vmaxv_s32
+//CIR-LABEL : @vmaxv_s32
+int32_t test_vmaxv_s32(int32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_S32_I]]
+ return vmaxv_s32(a);
+}
+
// LLVM-LABEL: @test_vmaxvq_s32(
// CIR-LABEL: @vmaxvq_s32(
int32_t test_vmaxvq_s32(int32x4_t a) {
@@ -138,6 +138,17 @@ uint16_t test_vmaxvq_u16(uint16x8_t a) {
return vmaxvq_u16(a);
}
+//LLVM-LABEL: @test_vmaxv_u32(
+//CIR-LABEL : @vmaxv_u32(
+uint32_t test_vmaxv_u32(uint32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_U32_I]]
+ return vmaxv_u32(a);
+}
+
// LLVM-LABEL: @test_vmaxvq_u32(
// CIR-LABEL: @vmaxvq_u32(
uint32_t test_vmaxvq_u32(uint32x4_t a) {
@@ -149,17 +160,6 @@ uint32_t test_vmaxvq_u32(uint32x4_t a) {
return vmaxvq_u32(a);
}
-//LLVM-LABEL: @test_vmaxvq_f64(
-//CIR-LABEL : @vmaxvq_f64(
-float64_t test_vmaxvq_f64(float64x2_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
-
-// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[A]])
-// LLVM: ret double [[VMAXVQ_F64_I]]
- return vmaxvq_f64(a);
-}
-
//LLVM-LABEL: @test_vmaxv_f32
//CIR-LABEL : @vmaxv_f32
float32_t test_vmaxv_f32(float32x2_t a) {
@@ -171,28 +171,29 @@ float32_t test_vmaxv_f32(float32x2_t a) {
return vmaxv_f32(a);
}
-//LLVM-LABEL: @test_vmaxv_u32(
-//CIR-LABEL : @vmaxv_u32(
-uint32_t test_vmaxv_u32(uint32x2_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
-
-// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]])
-// LLVM: ret i32 [[VMAXV_U32_I]]
- return vmaxv_u32(a);
+// LLVM-LABEL: @test_vmaxvq_f32(
+// CIR-LABEL: @vmaxvq_f32(
+float32_t test_vmaxvq_f32(float32x4_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
+
+// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])
+// LLVM: ret float [[VMAXVQ_F32_I]]
+ return vmaxvq_f32(a);
}
-//LLVM-LABEL: @test_vmaxv_s32
-//CIR-LABEL : @vmaxv_s32
-int32_t test_vmaxv_s32(int32x2_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
+//LLVM-LABEL: @test_vmaxvq_f64(
+//CIR-LABEL : @vmaxvq_f64(
+float64_t test_vmaxvq_f64(float64x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}}
-// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
-// LLVM: ret i32 [[VMAXV_S32_I]]
- return vmaxv_s32(a);
+// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[A]])
+// LLVM: ret double [[VMAXVQ_F64_I]]
+ return vmaxvq_f64(a);
}
+//===------------------------------------------------------===//
// 2.1.3.2 Vector Saturating Shift Left
//
// TODO: Implement the remaining intrinsics from this group.
>From 7bcfedf1226353c32e2b1ba10db75f75f7e9aad3 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Wed, 29 Apr 2026 01:14:11 -0400
Subject: [PATCH 7/8] Added the vmaxv_f16 variant and test cases for it
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 12 +++++++--
clang/test/CodeGen/AArch64/neon/intrinsics.c | 24 ++++++++++++++++-
.../CodeGen/AArch64/v8.2a-neon-intrinsics.c | 26 -------------------
3 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 41dda04a72159..b08736c9f7d2b 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2725,10 +2725,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vsqrtq_v:
assert(!cir::MissingFeatures::emitConstrainedFPCall());
return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc);
+ case NEON::BI__builtin_neon_vmaxv_f16: {
+ cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 4);
+ return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv",
+ fP16Ty, loc);
+ }
+ case NEON::BI__builtin_neon_vmaxvq_f16: {
+ cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 8);
+ return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv",
+ fP16Ty, loc);
+ }
case NEON::BI__builtin_neon_vrbit_v:
case NEON::BI__builtin_neon_vrbitq_v:
- case NEON::BI__builtin_neon_vmaxv_f16:
- case NEON::BI__builtin_neon_vmaxvq_f16:
case NEON::BI__builtin_neon_vminv_f16:
case NEON::BI__builtin_neon_vminvq_f16:
case NEON::BI__builtin_neon_vmaxnmv_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 95685912123fd..c1103f8a4faa3 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -1,6 +1,6 @@
// REQUIRES: aarch64-registered-target || arm-registered-target
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM
// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %}
// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %}
@@ -160,6 +160,28 @@ uint32_t test_vmaxvq_u32(uint32x4_t a) {
return vmaxvq_u32(a);
}
+// LLVM-LABEL: @test_vmaxv_f16(
+// CIR-LABEL: @test_vmaxv_f16(
+float16_t test_vmaxv_f16(float16x4_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<4 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <4 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxv_f16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_f16(
+// CIR-LABEL: cir.func {{.*}} @test_vmaxvq_f16
+float16_t test_vmaxvq_f16(float16x8_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<8 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <8 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxvq_f16(a);
+}
+
//LLVM-LABEL: @test_vmaxv_f32
//CIR-LABEL : @vmaxv_f32
float32_t test_vmaxv_f32(float32x2_t a) {
diff --git a/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c b/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
index b8380bd8ed6d4..64d3034fabec7 100644
--- a/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
@@ -2263,32 +2263,6 @@ float16_t test_vmulxh_laneq_f16(float16_t a, float16x8_t b) {
return vmulxh_laneq_f16(a, b, 7);
}
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_f16
-// CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[VMAXV:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
-// CHECK-NEXT: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[VMAXV]])
-// CHECK-NEXT: ret half [[VMAXV1]]
-//
-float16_t test_vmaxv_f16(float16x4_t a) {
- return vmaxv_f16(a);
-}
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f16
-// CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[VMAXV:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
-// CHECK-NEXT: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[VMAXV]])
-// CHECK-NEXT: ret half [[VMAXV1]]
-//
-float16_t test_vmaxvq_f16(float16x8_t a) {
- return vmaxvq_f16(a);
-}
-
// CHECK-LABEL: define {{[^@]+}}@test_vminv_f16
// CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
>From 13bfaf99457a0b3b67071e48b849efcf5326f830 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Wed, 29 Apr 2026 09:45:33 -0400
Subject: [PATCH 8/8] Moved the maximum test above and added the TODO
---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 50 +++++++++++---------
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index c1103f8a4faa3..805d5e272139d 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -24,6 +24,34 @@
#include <arm_neon.h>
+//===------------------------------------------------------===//
+// 2.6.1.7 Maximum
+//
+// TODO: Implement the remaining intrinsics from this group.
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vmaxv_f16(
+// CIR-LABEL: @test_vmaxv_f16(
+float16_t test_vmaxv_f16(float16x4_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<4 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <4 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxv_f16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_f16(
+// CIR-LABEL: cir.func {{.*}} @test_vmaxvq_f16
+float16_t test_vmaxvq_f16(float16x8_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<8 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <8 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxvq_f16(a);
+}
+
//===------------------------------------------------------===//
// 2.1.1.13 Maximum across vector
//===------------------------------------------------------===//
@@ -160,28 +188,6 @@ uint32_t test_vmaxvq_u32(uint32x4_t a) {
return vmaxvq_u32(a);
}
-// LLVM-LABEL: @test_vmaxv_f16(
-// CIR-LABEL: @test_vmaxv_f16(
-float16_t test_vmaxv_f16(float16x4_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<4 x !cir.f16>) -> !cir.f16
-
-// LLVM-SAME: <4 x half> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> {{.*}})
-// LLVM: ret half [[VMAXV1]]
- return vmaxv_f16(a);
-}
-
-// LLVM-LABEL: @test_vmaxvq_f16(
-// CIR-LABEL: cir.func {{.*}} @test_vmaxvq_f16
-float16_t test_vmaxvq_f16(float16x8_t a) {
-// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<8 x !cir.f16>) -> !cir.f16
-
-// LLVM-SAME: <8 x half> {{.*}}[[A:%.*]])
-// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> {{.*}})
-// LLVM: ret half [[VMAXV1]]
- return vmaxvq_f16(a);
-}
-
//LLVM-LABEL: @test_vmaxv_f32
//CIR-LABEL : @vmaxv_f32
float32_t test_vmaxv_f32(float32x2_t a) {
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