[clang] [CIR] max-across-vector (vmaxv_*) intrinsics (PR #194401)
Andrzej Warzyński via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 29 01:25:10 PDT 2026
================
@@ -24,6 +24,197 @@
#include <arm_neon.h>
+//===------------------------------------------------------===//
+// 2.1.1.13 Maximum across vector
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vmaxv_s8(
+// CIR-LABEL: @vmaxv_s8(
+int8_t test_vmaxv_s8(int8x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_s8({{%.*}}) : (!cir.vector<8 x !s8i> {{.*}}) -> !s8i
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]])
+// LLVM: ret i8 [[VMAXV_S8_I]]
+ return vmaxv_s8(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s8(
+// CIR-LABEL: @vmaxvq_s8(
+int8_t test_vmaxvq_s8(int8x16_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s8({{%.*}}) : (!cir.vector<16 x !s8i> {{.*}}) -> !s8i
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]])
+// LLVM: ret i8 [[VMAXVQ_S8_I]]
+ return vmaxvq_s8(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_s16(
+// CIR-LABEL: @vmaxv_s16(
+int16_t test_vmaxv_s16(int16x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_s16({{%.*}}) : (!cir.vector<4 x !s16i> {{.*}}) -> !s16i
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]])
+// LLVM: ret i16 [[VMAXV_S16_I]]
+ return vmaxv_s16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s16(
+// CIR-LABEL: @vmaxvq_s16(
+int16_t test_vmaxvq_s16(int16x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s16({{%.*}}) : (!cir.vector<8 x !s16i> {{.*}}) -> !s16i
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]])
+// LLVM: ret i16 [[VMAXVQ_S16_I]]
+ return vmaxvq_s16(a);
+}
+
+//LLVM-LABEL: @test_vmaxv_s32
+//CIR-LABEL : @vmaxv_s32
+int32_t test_vmaxv_s32(int32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_S32_I]]
+ return vmaxv_s32(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_s32(
+// CIR-LABEL: @vmaxvq_s32(
+int32_t test_vmaxvq_s32(int32x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_s32({{%.*}}) : (!cir.vector<4 x !s32i> {{.*}}) -> !s32i
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]])
+// LLVM: ret i32 [[VMAXVQ_S32_I]]
+ return vmaxvq_s32(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_u8(
+// CIR-LABEL: @vmaxv_u8(
+uint8_t test_vmaxv_u8(uint8x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_u8({{%.*}}) : (!cir.vector<8 x !u8i> {{.*}}) -> !u8i
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]])
+// LLVM: ret i8 [[VMAXV_U8_I]]
+ return vmaxv_u8(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u8(
+// CIR-LABEL: @vmaxvq_u8(
+uint8_t test_vmaxvq_u8(uint8x16_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u8({{%.*}}) : (!cir.vector<16 x !u8i> {{.*}}) -> !u8i
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]])
+// LLVM: ret i8 [[VMAXVQ_U8_I]]
+ return vmaxvq_u8(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_u16(
+// CIR-LABEL: @vmaxv_u16(
+uint16_t test_vmaxv_u16(uint16x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxv_u16({{%.*}}) : (!cir.vector<4 x !u16i> {{.*}}) -> !u16i
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]])
+// LLVM: ret i16 [[VMAXV_U16_I]]
+ return vmaxv_u16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u16(
+// CIR-LABEL: @vmaxvq_u16(
+uint16_t test_vmaxvq_u16(uint16x8_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u16({{%.*}}) : (!cir.vector<8 x !u16i> {{.*}}) -> !u16i
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]])
+// LLVM: ret i16 [[VMAXVQ_U16_I]]
+ return vmaxvq_u16(a);
+}
+
+//LLVM-LABEL: @test_vmaxv_u32(
+//CIR-LABEL : @vmaxv_u32(
+uint32_t test_vmaxv_u32(uint32x2_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}}
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]])
+// LLVM: ret i32 [[VMAXV_U32_I]]
+ return vmaxv_u32(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_u32(
+// CIR-LABEL: @vmaxvq_u32(
+uint32_t test_vmaxvq_u32(uint32x4_t a) {
+// CIR: {{%.*}} = cir.call @vmaxvq_u32({{%.*}}) : (!cir.vector<4 x !u32i> {{.*}}) -> !u32i
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]])
+// LLVM: ret i32 [[VMAXVQ_U32_I]]
+ return vmaxvq_u32(a);
+}
+
+// LLVM-LABEL: @test_vmaxv_f16(
+// CIR-LABEL: @test_vmaxv_f16(
+float16_t test_vmaxv_f16(float16x4_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<4 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <4 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxv_f16(a);
+}
+
+// LLVM-LABEL: @test_vmaxvq_f16(
+// CIR-LABEL: cir.func {{.*}} @test_vmaxvq_f16
+float16_t test_vmaxvq_f16(float16x8_t a) {
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} : (!cir.vector<8 x !cir.f16>) -> !cir.f16
+
+// LLVM-SAME: <8 x half> {{.*}}[[A:%.*]])
+// LLVM: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> {{.*}})
+// LLVM: ret half [[VMAXV1]]
+ return vmaxvq_f16(a);
----------------
banach-space wrote:
This intrinsic is from https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#maximum-2 rather than https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#maximum-across-vector that you were assigned.
I am happy for you to tackle both - but please group the intrinsics accordingly and update the summary to document that. Thank you!
https://github.com/llvm/llvm-project/pull/194401
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