[clang] [llvm] [AVX10] Remove use select instead of write mask argument (PR #194641)
via cfe-commits
cfe-commits at lists.llvm.org
Tue Apr 28 07:22:46 PDT 2026
https://github.com/mahesh-attarde created https://github.com/llvm/llvm-project/pull/194641
fixes https://github.com/llvm/llvm-project/issues/180695
>From 71e937177969e9b392d3a6ef9d62c7d72a9332e6 Mon Sep 17 00:00:00 2001
From: "Attarde, Mahesh" <mahesh.attarde at intel.com>
Date: Tue, 28 Apr 2026 07:21:38 -0700
Subject: [PATCH] [AVX10] Remove use select instead of write mask argument
---
clang/include/clang/Basic/BuiltinsX86.td | 6 ++--
clang/lib/Headers/avx10_2_512convertintrin.h | 17 +++++-----
clang/lib/Headers/avx10_2convertintrin.h | 33 ++++++++++---------
.../CodeGen/X86/avx10_2_512convert-builtins.c | 8 +++--
.../CodeGen/X86/avx10_2convert-builtins.c | 16 +++++----
llvm/include/llvm/IR/IntrinsicsX86.td | 12 +++----
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 9 -----
.../X86/avx10_2_512convert-intrinsics.ll | 11 ++++---
.../CodeGen/X86/avx10_2convert-intrinsics.ll | 29 +++++++++-------
9 files changed, 75 insertions(+), 66 deletions(-)
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index c8c371625b568..9f87c68a15cb6 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -4722,15 +4722,15 @@ let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>
}
let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
- def vcvtbiasph2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>, _Vector<16, char>, unsigned char)">;
+ def vcvtbiasph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>)">;
}
let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvtbiasph2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>, _Vector<16, char>, unsigned short)">;
+ def vcvtbiasph2bf8_256 : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>)">;
}
let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
- def vcvtbiasph2bf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>, _Vector<32, char>, unsigned int)">;
+ def vcvtbiasph2bf8_512 : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>)">;
}
let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in {
diff --git a/clang/lib/Headers/avx10_2_512convertintrin.h b/clang/lib/Headers/avx10_2_512convertintrin.h
index ffaed08cee798..de02c955de35a 100644
--- a/clang/lib/Headers/avx10_2_512convertintrin.h
+++ b/clang/lib/Headers/avx10_2_512convertintrin.h
@@ -59,22 +59,23 @@ _mm512_maskz_cvtx2ps_ph(__mmask32 __U, __m512 __A, __m512 __B) {
static __inline__ __m256i __DEFAULT_FN_ATTRS512
_mm512_cvtbiasph_bf8(__m512i __A, __m512h __B) {
- return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
- (__v64qi)__A, (__v32hf)__B, (__v32qi)_mm256_undefined_si256(),
- (__mmask32)-1);
+ return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512((__v64qi)__A, (__v32hf)__B);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtbiasph_bf8(
__m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
- return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
- (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (__mmask32)__U);
+ return (__m256i)__builtin_ia32_selectb_256(
+ (__mmask32)__U,
+ (__v32qi)__builtin_ia32_vcvtbiasph2bf8_512((__v64qi)__A, (__v32hf)__B),
+ (__v32qi)__W);
}
static __inline__ __m256i __DEFAULT_FN_ATTRS512
_mm512_maskz_cvtbiasph_bf8(__mmask32 __U, __m512i __A, __m512h __B) {
- return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
- (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)_mm256_setzero_si256(),
- (__mmask32)__U);
+ return (__m256i)__builtin_ia32_selectb_256(
+ (__mmask32)__U,
+ (__v32qi)__builtin_ia32_vcvtbiasph2bf8_512((__v64qi)__A, (__v32hf)__B),
+ (__v32qi)_mm256_setzero_si256());
}
static __inline__ __m256i __DEFAULT_FN_ATTRS512
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 2800ee73118d7..a5133258ebea4 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -293,8 +293,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
- (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
+ return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128((__v16qi)__A, (__v8hf)__B);
}
/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
@@ -333,8 +332,10 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
- (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U,
+ (__v16qi)__builtin_ia32_vcvtbiasph2bf8_128((__v16qi)__A, (__v8hf)__B),
+ (__v16qi)__W);
}
/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
@@ -371,9 +372,10 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
- (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
- (__mmask8)__U);
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U,
+ (__v16qi)__builtin_ia32_vcvtbiasph2bf8_128((__v16qi)__A, (__v8hf)__B),
+ (__v16qi)_mm_setzero_si128());
}
/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
@@ -401,9 +403,7 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// converted elements from \a __B using biases from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
- (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),
- (__mmask16)-1);
+ return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256((__v32qi)__A, (__v16hf)__B);
}
/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
@@ -441,8 +441,10 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
- (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U,
+ (__v16qi)__builtin_ia32_vcvtbiasph2bf8_256((__v32qi)__A, (__v16hf)__B),
+ (__v16qi)__W);
}
/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
@@ -478,9 +480,10 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
- (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
- (__mmask16)__U);
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U,
+ (__v16qi)__builtin_ia32_vcvtbiasph2bf8_256((__v32qi)__A, (__v16hf)__B),
+ (__v16qi)_mm_setzero_si128());
}
/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
diff --git a/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c b/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
index 7fbdcdc2d18c2..53b47db8cde09 100644
--- a/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
+++ b/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
@@ -43,19 +43,21 @@ __m512h test_mm512_maskz_cvtx_round2ps_ph(__mmask32 __U, __m512 __A, __m512 __B)
__m256i test_mm512_cvtbiasph_bf8(__m512i __A, __m512h __B) {
// CHECK-LABEL: @test_mm512_cvtbiasph_bf8(
- // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(
return _mm512_cvtbiasph_bf8(__A, __B);
}
__m256i test_mm512_mask_cvtbiasph_bf8(__m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
// CHECK-LABEL: @test_mm512_mask_cvtbiasph_bf8(
- // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(
+ // CHECK: call <32 x i8> @llvm.x86.avx512.select.v32i8(
return _mm512_mask_cvtbiasph_bf8(__W, __U, __A, __B);
}
__m256i test_mm512_maskz_cvtbiasph_bf8(__mmask32 __U, __m512i __A, __m512h __B) {
// CHECK-LABEL: @test_mm512_maskz_cvtbiasph_bf8(
- // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(
+ // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(
+ // CHECK: call <32 x i8> @llvm.x86.avx512.select.v32i8(
return _mm512_maskz_cvtbiasph_bf8(__U, __A, __B);
}
diff --git a/clang/test/CodeGen/X86/avx10_2convert-builtins.c b/clang/test/CodeGen/X86/avx10_2convert-builtins.c
index 025ab77b4bae6..0fc49ba1d547f 100644
--- a/clang/test/CodeGen/X86/avx10_2convert-builtins.c
+++ b/clang/test/CodeGen/X86/avx10_2convert-builtins.c
@@ -43,37 +43,41 @@ __m256h test_mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
__m128i test_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
// CHECK-LABEL: @test_mm_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(
return _mm_cvtbiasph_bf8(__A, __B);
}
__m128i test_mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
// CHECK-LABEL: @test_mm_mask_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(
+ // CHECK: call <16 x i8> @llvm.x86.avx512.select.v16i8(
return _mm_mask_cvtbiasph_bf8(__W, __U, __A, __B);
}
__m128i test_mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
// CHECK-LABEL: @test_mm_maskz_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(
+ // CHECK: call <16 x i8> @llvm.x86.avx512.select.v16i8(
return _mm_maskz_cvtbiasph_bf8(__U, __A, __B);
}
__m128i test_mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
// CHECK-LABEL: @test_mm256_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(
return _mm256_cvtbiasph_bf8(__A, __B);
}
__m128i test_mm256_mask_cvtbiasph_bf8(__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
// CHECK-LABEL: @test_mm256_mask_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(
+ // CHECK: call <16 x i8> @llvm.x86.avx512.select.v16i8(
return _mm256_mask_cvtbiasph_bf8(__W, __U, __A, __B);
}
__m128i test_mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
// CHECK-LABEL: @test_mm256_maskz_cvtbiasph_bf8(
- // CHECK: call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(
+ // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(
+ // CHECK: call <16 x i8> @llvm.x86.avx512.select.v16i8(
return _mm256_maskz_cvtbiasph_bf8(__U, __A, __B);
}
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index b75a0485d6263..9fbe7374b7c52 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -6915,14 +6915,14 @@ def int_x86_avx10_mask_vcvt2ps2phx_256 : ClangBuiltin<"__builtin_ia32_vcvt2ps2ph
def int_x86_avx10_mask_vcvt2ps2phx_512 : ClangBuiltin<"__builtin_ia32_vcvt2ps2phx512_mask">,
DefaultAttrsIntrinsic<[llvm_v32f16_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v32f16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<4>>]>;
-def int_x86_avx10_mask_vcvtbiasph2bf8128 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_128_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v8f16_ty, llvm_v16i8_ty, llvm_i8_ty],
+def int_x86_avx10_vcvtbiasph2bf8128 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_128">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v8f16_ty],
[IntrNoMem]>;
-def int_x86_avx10_mask_vcvtbiasph2bf8256 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_256_mask">,
- DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v16f16_ty, llvm_v16i8_ty, llvm_i16_ty],
+def int_x86_avx10_vcvtbiasph2bf8256 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_256">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v32i8_ty, llvm_v16f16_ty],
[IntrNoMem]>;
-def int_x86_avx10_mask_vcvtbiasph2bf8512 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_512_mask">,
- DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v64i8_ty, llvm_v32f16_ty, llvm_v32i8_ty, llvm_i32_ty],
+def int_x86_avx10_vcvtbiasph2bf8512 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8_512">,
+ DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v64i8_ty, llvm_v32f16_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_vcvtbiasph2bf8s128 : ClangBuiltin<"__builtin_ia32_vcvtbiasph2bf8s_128_mask">,
DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v8f16_ty, llvm_v16i8_ty, llvm_i8_ty],
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index c3e11fd1d5e42..08ac4ed21fe53 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1193,15 +1193,6 @@ def X86vcvtph2hf8 : SDNode<"X86ISD::VCVTPH2HF8",
SDTAVX10CONVERT_I8F16>;
def X86vcvtph2hf8s : SDNode<"X86ISD::VCVTPH2HF8S",
SDTAVX10CONVERT_I8F16>;
-
-def X86vmcvtbiasph2bf8 : SDNode<"X86ISD::VMCVTBIASPH2BF8",
- SDTAVX10CONVERT_2I8F16_MASK>;
-def X86vmcvtbiasph2bf8s : SDNode<"X86ISD::VMCVTBIASPH2BF8S",
- SDTAVX10CONVERT_2I8F16_MASK>;
-def X86vmcvtbiasph2hf8 : SDNode<"X86ISD::VMCVTBIASPH2HF8",
- SDTAVX10CONVERT_2I8F16_MASK>;
-def X86vmcvtbiasph2hf8s : SDNode<"X86ISD::VMCVTBIASPH2HF8S",
- SDTAVX10CONVERT_2I8F16_MASK>;
def X86vmcvtph2bf8 : SDNode<"X86ISD::VMCVTPH2BF8",
SDTAVX10CONVERT_I8F16_MASK>;
def X86vmcvtph2bf8s : SDNode<"X86ISD::VMCVTPH2BF8S",
diff --git a/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll
index cc87ae0aad1f5..b33d149e32c31 100644
--- a/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll
@@ -91,7 +91,7 @@ define <32 x i8> @test_int_x86_avx10_vcvtbiasph2bf8512(<64 x i8> %A, <32 x half>
; CHECK: # %bb.0:
; CHECK-NEXT: vcvtbiasph2bf8 %zmm1, %zmm0, %ymm0 # encoding: [0x62,0xf2,0x7c,0x48,0x74,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %ret = call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B, <32 x i8> undef, i32 -1)
+ %ret = call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B)
ret <32 x i8> %ret
}
@@ -107,11 +107,13 @@ define <32 x i8> @test_int_x86_avx10_mask_vcvtbiasph2bf8512(<32 x i8> %W, i32 %U
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvtbiasph2bf8 %zmm2, %zmm1, %ymm0 {%k1} # encoding: [0x62,0xf2,0x74,0x49,0x74,0xc2]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B, <32 x i8> %W, i32 %U)
+ %conv = call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B)
+ %ret = call <32 x i8> @llvm.x86.avx512.select.v32i8(i32 %U, <32 x i8> %conv, <32 x i8> %W)
ret <32 x i8> %ret
}
-declare <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B, <32 x i8> %W, i32 %U)
+declare <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B)
+declare <32 x i8> @llvm.x86.avx512.select.v32i8(i32, <32 x i8>, <32 x i8>)
define <32 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B, i32 %U) nounwind {
; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasph2bf8512:
@@ -125,7 +127,8 @@ define <32 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8512(<64 x i8> %A, <32 x
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvtbiasph2bf8 %zmm1, %zmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x7c,0xc9,0x74,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <32 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B, <32 x i8> zeroinitializer, i32 %U)
+ %conv = call <32 x i8> @llvm.x86.avx10.vcvtbiasph2bf8512(<64 x i8> %A, <32 x half> %B)
+ %ret = call <32 x i8> @llvm.x86.avx512.select.v32i8(i32 %U, <32 x i8> %conv, <32 x i8> zeroinitializer)
ret <32 x i8> %ret
}
diff --git a/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll
index 04c93eb1ee6d0..eeab99f5464ed 100644
--- a/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll
@@ -93,11 +93,11 @@ define <16 x i8> @test_int_x86_avx10_vcvtbiasph2bf8128(<16 x i8> %A, <8 x half>
; CHECK: # %bb.0:
; CHECK-NEXT: vcvtbiasph2bf8 %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7c,0x08,0x74,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, <16 x i8> undef, i8 -1)
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B)
ret <16 x i8> %ret
}
-define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasph2bf8128(<16 x i8> %W, <16 x i8> %A, <8 x half> %B, i8 %U) nounwind {
+define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasph2bf8128(<16 x i8> %W, <16 x i8> %A, <8 x half> %B, i16 %U) nounwind {
; X64-LABEL: test_int_x86_avx10_mask_vcvtbiasph2bf8128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
@@ -106,16 +106,18 @@ define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasph2bf8128(<16 x i8> %W, <16 x
;
; X86-LABEL: test_int_x86_avx10_mask_vcvtbiasph2bf8128:
; X86: # %bb.0:
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvtbiasph2bf8 %xmm2, %xmm1, %xmm0 {%k1} # encoding: [0x62,0xf2,0x74,0x09,0x74,0xc2]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, <16 x i8> %W, i8 %U)
+ %conv = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B)
+ %ret = call <16 x i8> @llvm.x86.avx512.select.v16i8(i16 %U, <16 x i8> %conv, <16 x i8> %W)
ret <16 x i8> %ret
}
-declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, <16 x i8> %W, i8 %U)
+declare <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B)
+declare <16 x i8> @llvm.x86.avx512.select.v16i8(i16, <16 x i8>, <16 x i8>)
-define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, i8 %U) nounwind {
+define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, i16 %U) nounwind {
; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasph2bf8128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
@@ -124,10 +126,11 @@ define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8128(<16 x i8> %A, <8 x
;
; X86-LABEL: test_int_x86_avx10_maskz_vcvtbiasph2bf8128:
; X86: # %bb.0:
-; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvtbiasph2bf8 %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7c,0x89,0x74,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B, <16 x i8> zeroinitializer, i8 %U)
+ %conv = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8128(<16 x i8> %A, <8 x half> %B)
+ %ret = call <16 x i8> @llvm.x86.avx512.select.v16i8(i16 %U, <16 x i8> %conv, <16 x i8> zeroinitializer)
ret <16 x i8> %ret
}
@@ -137,7 +140,7 @@ define <16 x i8> @test_int_x86_avx10_vcvtbiasph2bf8256(<32 x i8> %A, <16 x half>
; CHECK-NEXT: vcvtbiasph2bf8 %ymm1, %ymm0, %xmm0 # encoding: [0x62,0xf2,0x7c,0x28,0x74,0xc1]
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B, <16 x i8> undef, i16 -1)
+ %ret = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B)
ret <16 x i8> %ret
}
@@ -155,11 +158,12 @@ define <16 x i8> @test_int_x86_avx10_mask_vcvtbiasph2bf8256(<16 x i8> %W, <32 x
; X86-NEXT: vcvtbiasph2bf8 %ymm2, %ymm1, %xmm0 {%k1} # encoding: [0x62,0xf2,0x74,0x29,0x74,0xc2]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B, <16 x i8> %W, i16 %U)
+ %conv = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B)
+ %ret = call <16 x i8> @llvm.x86.avx512.select.v16i8(i16 %U, <16 x i8> %conv, <16 x i8> %W)
ret <16 x i8> %ret
}
-declare <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B, <16 x i8> %W, i16 %U)
+declare <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B)
define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B, i16 %U) nounwind {
; X64-LABEL: test_int_x86_avx10_maskz_vcvtbiasph2bf8256:
@@ -175,7 +179,8 @@ define <16 x i8> @test_int_x86_avx10_maskz_vcvtbiasph2bf8256(<32 x i8> %A, <16 x
; X86-NEXT: vcvtbiasph2bf8 %ymm1, %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7c,0xa9,0x74,0xc1]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %ret = call <16 x i8> @llvm.x86.avx10.mask.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B, <16 x i8> zeroinitializer, i16 %U)
+ %conv = call <16 x i8> @llvm.x86.avx10.vcvtbiasph2bf8256(<32 x i8> %A, <16 x half> %B)
+ %ret = call <16 x i8> @llvm.x86.avx512.select.v16i8(i16 %U, <16 x i8> %conv, <16 x i8> zeroinitializer)
ret <16 x i8> %ret
}
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