[clang] [llvm] [aarch64] Add more MSVC intrinsics (atomic part) (PR #194635)
Adhemerval Zanella via cfe-commits
cfe-commits at lists.llvm.org
Tue Apr 28 06:57:18 PDT 2026
https://github.com/zatrazz created https://github.com/llvm/llvm-project/pull/194635
This patchset adds more intrinsics from MSVC build 2026 [1]. I focused on the one documented by Microsoft, although intrin.h and related headers do export more symbols.
This is split from https://github.com/llvm/llvm-project/pull/193221 , and it contains the atomic operations that might require more discussion on how to expose them.
MSVC exports them without tying to any ISA/extension requirements (the /arch: option is ignored), and the idea is to use them in the same manner as inline assembly (which MSVC has limited support for). I am not sure if this is the preferred approach for clang, since it already has intrin.h implying on arm_acle.h inclusion, and it already exports some built-ins that MSVC supports, with the target attribute set (like __crc32X and __rndr).
>From 12677e8e93f8dd7eda81f9af318d86da1f336a6b Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Mon, 13 Apr 2026 16:04:27 -0300
Subject: [PATCH 01/20] [aarch64] Add support for the __ldar{8|16|32|64} MS
intrinsics (#121689)
Adds support for the following MSVC intrinsics:
* `__ldar8` - maps to LDARB
* `__ldar16` - maps to LDARH
* `__ldar32` - maps to LDAR
* `__ldar64` - maps to LDAR
The emit is done using SeqCst atomic operations because wth RCPC enabled
the AArch64 backend lower acquire loads to LDARP* instead of LDAR*.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 7 ++++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 17 ++++++++++
clang/lib/Headers/arm64intr.h | 13 ++++++++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 32 +++++++++++++++++++
4 files changed, 69 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 8e5dbb5f4172d..f9e6fdd1492f8 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -403,3 +403,10 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", Header = "intrin.h" in {
def __hlt : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">;
}
+
+let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", Header = "intrin.h" in {
+ def __ldar8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char const volatile *)">;
+ def __ldar16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short const volatile *)">;
+ def __ldar32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int const volatile *)">;
+ def __ldar64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int const volatile*)">;
+}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index f8d383b15313f..9b3d546b8fe7d 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5253,6 +5253,23 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return ConstantInt::get(Builder.getInt32Ty(), 0);
}
+ if (BuiltinID == AArch64::BI__ldar8 || BuiltinID == AArch64::BI__ldar16 ||
+ BuiltinID == AArch64::BI__ldar32 || BuiltinID == AArch64::BI__ldar64) {
+ Value *Ptr = EmitScalarExpr(E->getArg(0));
+ QualType ElTy = E->getArg(0)->getType()->getPointeeType();
+ CharUnits LoadSize = CGM.getContext().getTypeSizeInChars(ElTy);
+ llvm::Type *ITy =
+ llvm::IntegerType::get(getLLVMContext(), LoadSize.getQuantity() * 8);
+ llvm::LoadInst *Load = Builder.CreateAlignedLoad(ITy, Ptr, LoadSize);
+ // We need SeqCst instead of Acquire because with RCPC enabled the AArch64
+ // lowers Acquire loads to LDARP* instead of LDAR*. The SeqCst has not RCPC
+ // override and always maps to LDAR*. This is the same apprach used by
+ // __iso_volatile_load (which uses Monotonic plus volatile for plain ldr).
+ Load->setAtomic(llvm::AtomicOrdering::SequentiallyConsistent);
+ Load->setVolatile(true);
+ return Load;
+ }
+
if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32)
return Builder.CreateFPTrunc(
Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 4943b2db69d02..58629d7b0f1b1 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -31,5 +31,18 @@ typedef enum
_ARM64_BARRIER_OSHLD = 0x1
} _ARM64INTR_BARRIER_TYPE;
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+unsigned __int8 __ldar8(const volatile unsigned __int8 *);
+unsigned __int16 __ldar16(const volatile unsigned __int16 *);
+unsigned __int32 __ldar32(const volatile unsigned __int32 *);
+unsigned __int64 __ldar64(const volatile unsigned __int64 *);
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __ARM64INTR_H */
#endif /* _MSC_VER */
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 2f5ab50d6c848..6a10e4f43afcd 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -595,5 +595,37 @@ void check__prefetch(void *arg1) {
// CHECK-MSCOMPAT: ret void
+unsigned char check__ldar8(unsigned char volatile *p) {
+ return __ldar8(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @check__ldar8(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = load atomic volatile i8, ptr %{{.*}} seq_cst, align 1
+// CHECK-MSCOMPAT: ret i8 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldar8'
+
+unsigned short check__ldar16(unsigned short volatile *p) {
+ return __ldar16(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @check__ldar16(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = load atomic volatile i16, ptr %{{.*}} seq_cst, align 2
+// CHECK-MSCOMPAT: ret i16 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldar16'
+
+unsigned int check__ldar32(unsigned int volatile *p) {
+ return __ldar32(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @check__ldar32(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = load atomic volatile i32, ptr %{{.*}} seq_cst, align 4
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldar32'
+
+unsigned long long int check__ldar64(unsigned long long int volatile *p) {
+ return __ldar64(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @check__ldar64(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = load atomic volatile i64, ptr %{{.*}} seq_cst, align 8
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldar64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 95db0f64d1cd87fcde821b53d03b0b404574c6b2 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Wed, 15 Apr 2026 09:43:49 -0300
Subject: [PATCH 02/20] [aarch64] Add support for the __stlr{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__stlr8` - maps to STLRB.
* `__stlr16` - maps to STLRH.
* `__stlr32` - maps to STLR.
* `__stlr64` - maps to STLR.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 12 +++++
clang/lib/Headers/arm64intr.h | 5 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 44 +++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index f9e6fdd1492f8..28973c1b1f71e 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -409,4 +409,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __ldar16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short const volatile *)">;
def __ldar32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int const volatile *)">;
def __ldar64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int const volatile*)">;
+ def __stlr8 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned char volatile *, unsigned char)">;
+ def __stlr16 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned short volatile *, unsigned short)">;
+ def __stlr32 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned int volatile *, unsigned int)">;
+ def __stlr64 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned long long int volatile *, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 9b3d546b8fe7d..fe2a112e5631c 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5270,6 +5270,18 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Load;
}
+ if (BuiltinID == AArch64::BI__stlr8 || BuiltinID == AArch64::BI__stlr16 ||
+ BuiltinID == AArch64::BI__stlr32 || BuiltinID == AArch64::BI__stlr64) {
+ Value *Ptr = EmitScalarExpr(E->getArg(0));
+ Value *Val = EmitScalarExpr(E->getArg(1));
+ QualType ElTy = E->getArg(0)->getType()->getPointeeType();
+ CharUnits StoreSize = CGM.getContext().getTypeSizeInChars(ElTy);
+ llvm::StoreInst *Store = Builder.CreateAlignedStore(Val, Ptr, StoreSize);
+ Store->setAtomic(llvm::AtomicOrdering::Release);
+ Store->setVolatile(true);
+ return Store;
+ }
+
if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32)
return Builder.CreateFPTrunc(
Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 58629d7b0f1b1..53dca5fcc14e6 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -40,6 +40,11 @@ unsigned __int16 __ldar16(const volatile unsigned __int16 *);
unsigned __int32 __ldar32(const volatile unsigned __int32 *);
unsigned __int64 __ldar64(const volatile unsigned __int64 *);
+void __stlr8(unsigned __int8 volatile *, unsigned __int8);
+void __stlr16(unsigned __int16 volatile *, unsigned __int16);
+void __stlr32(unsigned __int32 volatile *, unsigned __int32);
+void __stlr64(unsigned __int64 volatile *, unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 6a10e4f43afcd..f800fc071ef5c 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -627,5 +627,49 @@ unsigned long long int check__ldar64(unsigned long long int volatile *p) {
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__ldar64'
+void test__stlr8(unsigned __int8 volatile *p, unsigned __int8 v)
+{
+ __stlr8 (p, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}void @test__stlr8(ptr{{.*}}%p, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[DEST:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[VALUE:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: store atomic volatile i8 %[[VALUE]], ptr %[[DEST]] release, align 1
+// CHECK-MSCOMPAT: ret void
+// CHECK-LINUX: error: call to undeclared function '__stlr8'
+
+void test__stlr16(unsigned __int16 volatile *p, unsigned __int16 v)
+{
+ __stlr16 (p, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}void @test__stlr16(ptr{{.*}}%p, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[DEST:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[VALUE:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: store atomic volatile i16 %[[VALUE]], ptr %[[DEST]] release, align 2
+// CHECK-MSCOMPAT: ret void
+// CHECK-LINUX: error: call to undeclared function '__stlr16'
+
+void test__stlr32(unsigned __int32 volatile *p, unsigned __int32 v)
+{
+ __stlr32(p, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}void @test__stlr32(ptr{{.*}}%p, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[DEST:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[VALUE:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: store atomic volatile i32 %[[VALUE]], ptr %[[DEST]] release, align 4
+// CHECK-MSCOMPAT: ret void
+// CHECK-LINUX: error: call to undeclared function '__stlr32'
+
+void test__stlr64(unsigned __int64 volatile *p, unsigned __int64 v)
+{
+ __stlr64(p, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}void @test__stlr64(ptr{{.*}}%p, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[DEST:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[VALUE:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: store atomic volatile i64 %[[VALUE]], ptr %[[DEST]] release, align 8
+// CHECK-MSCOMPAT: ret void
+// CHECK-LINUX: error: call to undeclared function '__stlr64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 3c8ac2c802b4037a996e0996a6f1fb601e7a2b8b Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Wed, 22 Apr 2026 16:26:44 -0300
Subject: [PATCH 03/20] [aarch64] Add support for ldarp builtin
The new intrinsic issues LDAPR* instruction directly, regardless of RCPC
target features. This will be used to implement MSVC __ldaprX builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 ++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 7 +++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ++++
.../CodeGen/AArch64/ms-intrinsics-ldapr.ll | 46 +++++++++++++++++++
4 files changed, 76 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/ms-intrinsics-ldapr.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index ccc2fe06ec0d2..65bd20d438c59 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -34,6 +34,21 @@ def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
def int_aarch64_clrex : Intrinsic<[]>;
+// LDAPR intrinsics — emit LDAPR* directly, regardless of RCPC target feature.
+// LDAPRB/H/W return i32 (zero-extended into GPR32); LDAPRX returns i64.
+def int_aarch64_ldapr8 : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
+ [IntrNoFree, IntrWillReturn,
+ IntrReadMem, IntrArgMemOnly]>;
+def int_aarch64_ldapr16 : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
+ [IntrNoFree, IntrWillReturn,
+ IntrReadMem, IntrArgMemOnly]>;
+def int_aarch64_ldapr32 : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
+ [IntrNoFree, IntrWillReturn,
+ IntrReadMem, IntrArgMemOnly]>;
+def int_aarch64_ldapr64 : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
+ [IntrNoFree, IntrWillReturn,
+ IntrReadMem, IntrArgMemOnly]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 2187f21abb70f..be3a8cf819e90 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -60,6 +60,13 @@ let Predicates = [HasRCPC] in {
def : Pat<(acquiring_load<atomic_load_nonext_64> GPR64sp:$ptr), (LDAPRX GPR64sp:$ptr)>;
}
+// Unconditional patterns for the __ldapr* MSVC builtins. These force LDAPR*
+// emission regardless of the RCPC subtarget feature.
+def : Pat<(i32 (int_aarch64_ldapr8 GPR64sp:$Rn)), (LDAPRB_cg GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_ldapr16 GPR64sp:$Rn)), (LDAPRH_cg GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_ldapr32 GPR64sp:$Rn)), (LDAPRW_cg GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_ldapr64 GPR64sp:$Rn)), (LDAPRX_cg GPR64sp:$Rn)>;
+
// 8-bit loads
def : Pat<(seq_cst_load<atomic_load_azext_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
def : Pat<(acquiring_load<atomic_load_azext_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f20f978fe7e8a..9c1c2db484888 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1930,6 +1930,14 @@ let Predicates = [HasRCPC] in {
def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
}
+// Code-gen-only LDAPR variants for the __ldapr* MSVC builtins.
+let isCodeGenOnly = 1 in {
+ def LDAPRB_cg : RCPCLoad<0b00, "ldaprb", GPR32>;
+ def LDAPRH_cg : RCPCLoad<0b01, "ldaprh", GPR32>;
+ def LDAPRW_cg : RCPCLoad<0b10, "ldapr", GPR32>;
+ def LDAPRX_cg : RCPCLoad<0b11, "ldapr", GPR64>;
+}
+
// v8.3a complex add and multiply-accumulate. No predicate here, that is done
// inside the multiclass as the FP16 versions need different predicates.
defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop,
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-ldapr.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-ldapr.ll
new file mode 100644
index 0000000000000..1c1073a16bdb9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-ldapr.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-windows-msvc -fast-isel=0 -global-isel=false \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-windows-msvc -mattr=+rcpc -fast-isel=0 \
+; RUN: -global-isel=false -verify-machineinstrs < %s | FileCheck %s
+
+; Tests for the __ldapr* MS builtins on AArch64. These lower to the
+; llvm.aarch64.ldaprN intrinsics and must select ldaprb/h/w/x regardless
+; of whether +rcpc is present in the target features (the _cg ISel variants
+; have no feature predicate).
+
+define i32 @test_ldapr8(ptr %p) {
+; CHECK-LABEL: test_ldapr8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldaprb w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.ldapr8(ptr %p)
+ ret i32 %r
+}
+
+define i32 @test_ldapr16(ptr %p) {
+; CHECK-LABEL: test_ldapr16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldaprh w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.ldapr16(ptr %p)
+ ret i32 %r
+}
+
+define i32 @test_ldapr32(ptr %p) {
+; CHECK-LABEL: test_ldapr32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldapr w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.ldapr32(ptr %p)
+ ret i32 %r
+}
+
+define i64 @test_ldapr64(ptr %p) {
+; CHECK-LABEL: test_ldapr64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldapr x0, [x0]
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.ldapr64(ptr %p)
+ ret i64 %r
+}
\ No newline at end of file
>From 11249c59ee5d19eb177831c39a1db634e7bc4140 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Tue, 14 Apr 2026 11:27:39 -0300
Subject: [PATCH 04/20] [aarch64] Add support for the __ldapr{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__ldapr8` - LDAPRB
* `__ldapr16` - LDAPRH
* `__ldapr32` - LDAPR
* `__ldapr64` - LDAPR
The emit is done using new intrisincs to issue LDAPR* instruction
directly, regardless of RCPC target features. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 26 +++++++++++++
clang/lib/Headers/arm64intr.h | 5 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 38 +++++++++++++++++++
4 files changed, 73 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 28973c1b1f71e..545829cc5ae83 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -413,4 +413,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __stlr16 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned short volatile *, unsigned short)">;
def __stlr32 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned int volatile *, unsigned int)">;
def __stlr64 : AArch64NoPrefixTargetLibBuiltin<"void (unsigned long long int volatile *, unsigned long long int)">;
+ def __ldapr8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char const volatile *)">;
+ def __ldapr16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short const volatile *)">;
+ def __ldapr32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int const volatile *)">;
+ def __ldapr64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int const volatile *)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index fe2a112e5631c..86cf503ec6de1 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5282,6 +5282,32 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Store;
}
+ if (BuiltinID == AArch64::BI__ldapr8 || BuiltinID == AArch64::BI__ldapr16 ||
+ BuiltinID == AArch64::BI__ldapr32 || BuiltinID == AArch64::BI__ldapr64) {
+ unsigned IntrID;
+ switch (BuiltinID) {
+ case AArch64::BI__ldapr8:
+ IntrID = Intrinsic::aarch64_ldapr8;
+ break;
+ case AArch64::BI__ldapr16:
+ IntrID = Intrinsic::aarch64_ldapr16;
+ break;
+ case AArch64::BI__ldapr32:
+ IntrID = Intrinsic::aarch64_ldapr32;
+ break;
+ default:
+ IntrID = Intrinsic::aarch64_ldapr64;
+ break;
+ }
+ Value *Ptr = EmitScalarExpr(E->getArg(0));
+ Value *Result = Builder.CreateCall(CGM.getIntrinsic(IntrID), Ptr);
+ // LDAPRB/H return i32 (zero-extended); truncate to match the declared type.
+ llvm::Type *RetTy = ConvertType(E->getType());
+ if (Result->getType() != RetTy)
+ Result = Builder.CreateTrunc(Result, RetTy);
+ return Result;
+ }
+
if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32)
return Builder.CreateFPTrunc(
Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 53dca5fcc14e6..a0c62c2fc7775 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -40,6 +40,11 @@ unsigned __int16 __ldar16(const volatile unsigned __int16 *);
unsigned __int32 __ldar32(const volatile unsigned __int32 *);
unsigned __int64 __ldar64(const volatile unsigned __int64 *);
+unsigned __int8 __ldapr8(const volatile unsigned __int8 *);
+unsigned __int16 __ldapr16(const volatile unsigned __int16 *);
+unsigned __int32 __ldapr32(const volatile unsigned __int32 *);
+unsigned __int64 __ldapr64(const volatile unsigned __int64 *);
+
void __stlr8(unsigned __int8 volatile *, unsigned __int8);
void __stlr16(unsigned __int16 volatile *, unsigned __int16);
void __stlr32(unsigned __int32 volatile *, unsigned __int32);
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index f800fc071ef5c..6af7cd9adad24 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -671,5 +671,43 @@ void test__stlr64(unsigned __int64 volatile *p, unsigned __int64 v)
// CHECK-MSCOMPAT: ret void
// CHECK-LINUX: error: call to undeclared function '__stlr64'
+unsigned char check__ldapr8(unsigned char volatile *p) {
+ return __ldapr8(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @check__ldapr8(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[LOAD:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[TMP:[0-9]+]] = call i32 @llvm.aarch64.ldapr8(ptr %[[LOAD]])
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = trunc i32 %[[TMP]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldapr8'
+
+unsigned short check__ldapr16(unsigned short volatile *p) {
+ return __ldapr16(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @check__ldapr16(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[LOAD:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[TMP:[0-9]+]] = call i32 @llvm.aarch64.ldapr16(ptr %[[LOAD]])
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = trunc i32 %[[TMP]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldapr16'
+
+unsigned int check__ldapr32(unsigned int volatile *p) {
+ return __ldapr32(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @check__ldapr32(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[LOAD:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.ldapr32(ptr %[[LOAD]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldapr32'
+
+unsigned long long int check__ldapr64(unsigned long long int volatile *p) {
+ return __ldapr64(p);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @check__ldapr64(ptr{{.*}}%p){{.*}}{
+// CHECK-MSCOMPAT: %[[LOAD:[0-9]+]] = load ptr, ptr %p.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.ldapr64(ptr %[[LOAD]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__ldapr64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 95e6277c0c1f6dca35beb60cb8b7c9e60b3bb1d9 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 10:52:29 -0300
Subject: [PATCH 05/20] [aarch64] Add support for cas builtin
The new intrinsic issues CAS* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __casX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 ++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 19 +++++++
.../lib/Target/AArch64/AArch64InstrFormats.td | 23 ++++++---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 +++
.../test/CodeGen/AArch64/ms-intrinsics-cas.ll | 50 +++++++++++++++++++
5 files changed, 106 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 65bd20d438c59..1e513520ea99e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -49,6 +49,21 @@ def int_aarch64_ldapr64 : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
[IntrNoFree, IntrWillReturn,
IntrReadMem, IntrArgMemOnly]>;
+// CAS intrinsics — emit CAS* (no acquire/release) directly, regardless of the
+// LSE target feature. CAS{H,b} comparand/value use i32; CAS{X}uses i64.
+def int_aarch64_cas8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_cas16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_cas32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_cas64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index be3a8cf819e90..7fbcf20c64409 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -575,6 +575,25 @@ let Predicates = [HasLSFE] in {
defm : LDBFPOPregister_patterns<"LDBFMIN", "atomic_load_fminimum">;
}
+// Unconditional patterns for the __cas* MSVC builtins to emit CAS* regardless
+// of the LSE subtarget feature. cas{b,h} use only the low bits of the
+// comparison register, so the zero extension masking emitted by CodeGen
+// (zext i8/i16 -> i32 -> 'and w,w,#mask') is redundant.
+def : Pat<(i32 (int_aarch64_cas8 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 255)), (and GPR32:$Rt, (i32 255)))),
+ (CASB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_cas8 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_cas16 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 65535)), (and GPR32:$Rt, (i32 65535)))),
+ (CASH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_cas16 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_cas32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASW_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_cas64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
+ (CASX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 894c36b8071ad..ae05efc43dec3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12383,7 +12383,7 @@ class CryptoRRRi2Tied<bits<1>op0, bits<2>op1, string asm>
// ST<OP>{<order>}[<size>] <Ws>, [<Xn|SP>]
// ST<OP>{<order>} <Xs>, [<Xn|SP>]
-let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
+let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
string cstr, list<dag> pattern>
: I<oops, iops, asm, operands, cstr, pattern> {
@@ -12404,7 +12404,6 @@ class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
let Inst{14-10} = 0b11111;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
- let Predicates = [HasLSE];
}
class BaseCAS<string order, string size, RegisterClass RC>
@@ -12415,13 +12414,23 @@ class BaseCAS<string order, string size, RegisterClass RC>
let NP = 1;
}
-multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order> {
- let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseCAS<order, "b", GPR32>;
- let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseCAS<order, "h", GPR32>;
- let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseCAS<order, "", GPR32>;
- let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseCAS<order, "", GPR64>;
+multiclass CompareAndSwap_impl<bits<1> Acq, bits<1> Rel, string order, list<Predicate> preds, string suffix> {
+ let Predicates = preds, Acq = Acq, Rel = Rel in {
+ let Sz = 0b00 in def "B" # suffix : BaseCAS<order, "b", GPR32>;
+ let Sz = 0b01 in def "H" # suffix : BaseCAS<order, "h", GPR32>;
+ let Sz = 0b10 in def "W" # suffix : BaseCAS<order, "", GPR32>;
+ let Sz = 0b11 in def "X" # suffix : BaseCAS<order, "", GPR64>;
+ }
}
+multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order>
+ : CompareAndSwap_impl<Acq, Rel, order, [HasLSE], "">;
+
+// For isCodeGenOnly use by MS intrinsics that must emit CAS* regardless
+// of the -march setting.
+multiclass CompareAndSwap_cg<bits<1> Acq, bits<1> Rel, string order>
+ : CompareAndSwap_impl<Acq, Rel, order, [], "_cg">;
+
class BaseCASP<string order, string size, RegisterOperand RC>
: BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
"casp" # order # size, "\t$Rs, $Rt, [$Rn]",
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 9c1c2db484888..c6cc76844b11d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3031,6 +3031,12 @@ defm CASA : CompareAndSwap<1, 0, "a">;
defm CASL : CompareAndSwap<0, 1, "l">;
defm CASAL : CompareAndSwap<1, 1, "al">;
+// isCodeGenOnly=1: excluded from asm parser/disassembler, no HasLSE predicate.
+// Used by the __cas* MS intrinsics to force CAS* emission regardless of -march.
+let isCodeGenOnly = 1 in {
+ defm CAS : CompareAndSwap_cg<0, 0, "">;
+}
+
// v8.1 atomic CASP
defm CASP : CompareAndSwapPair<0, 0, "">;
defm CASPA : CompareAndSwapPair<1, 0, "a">;
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
new file mode 100644
index 0000000000000..b3ee250bd96c3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel=0 -global-isel=false \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+lse -fast-isel=0 \
+; RUN: -global-isel=false -verify-machineinstrs < %s | FileCheck %s
+
+; Tests for the __cas* MS builtins on AArch64. These lower to
+; llvm.aarch64.cas* intrinsics and must select the corresponding CAS instruction
+; regardless of whether +lse is present in the target features (the _cg ISel
+; variants have no feature predicate).
+
+define i32 @test_cas8(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_cas8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casb w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.cas8(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_cas16(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_cas16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cash w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.cas16(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_cas32(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_cas32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cas w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.cas32(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i64 @test_cas64(ptr %p, i64 %rs, i64 %rt) {
+; CHECK-LABEL: test_cas64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cas x1, x2, [x0]
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.cas64(ptr %p, i64 %rs, i64 %rt)
+ ret i64 %r
+}
\ No newline at end of file
>From 2927a843d1822fb62b1ae1c6eb3c70461b966df5 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Wed, 15 Apr 2026 16:53:14 -0300
Subject: [PATCH 06/20] [aarch64] Add support for the __cas{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__cas8` - maps to CASB.
* `__cas16` - maps to CASH.
* `__cas32` - maps to CAS.
* `__cas64` - maps to CAS.
The emit is done using new intrisincs to issue CAS* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 5 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 41 ++++++++++++++
clang/lib/Headers/arm64intr.h | 9 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 56 +++++++++++++++++++
4 files changed, 111 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 545829cc5ae83..8d1dd4aea6b03 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -417,4 +417,9 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __ldapr16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short const volatile *)">;
def __ldapr32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int const volatile *)">;
def __ldapr64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int const volatile *)">;
+
+ def __cas8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char, unsigned char)">;
+ def __cas16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
+ def __cas32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
+ def __cas64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 86cf503ec6de1..bdcea53f508f1 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5308,6 +5308,47 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Result;
}
+ if (BuiltinID == AArch64::BI__cas8 || BuiltinID == AArch64::BI__cas16 ||
+ BuiltinID == AArch64::BI__cas32 || BuiltinID == AArch64::BI__cas64) {
+ unsigned IntrID;
+ llvm::Type *IntrArgTy;
+ switch (BuiltinID) {
+ case AArch64::BI__cas8:
+ IntrID = Intrinsic::aarch64_cas8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__cas16:
+ IntrID = Intrinsic::aarch64_cas16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__cas32:
+ IntrID = Intrinsic::aarch64_cas32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__cas64:
+ IntrID = Intrinsic::aarch64_cas64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
+ default:
+ llvm_unreachable("missing builtin ID in switch!");
+ }
+ Value *Ptr = EmitScalarExpr(E->getArg(0));
+ Value *Comp = EmitScalarExpr(E->getArg(1));
+ Value *Val = EmitScalarExpr(E->getArg(2));
+ // For 8/16-bit we need to zext to GRP size
+ if (Comp->getType() != IntrArgTy)
+ Comp = Builder.CreateZExt(Comp, IntrArgTy);
+ if (Val->getType() != IntrArgTy)
+ Val = Builder.CreateZExt(Val, IntrArgTy);
+ Value *Result =
+ Builder.CreateCall(CGM.getIntrinsic(IntrID), {Ptr, Comp, Val});
+ // CAS{B/H} return i32 (zero-extended); truncate to declared type.
+ llvm::Type *RetTy = ConvertType(E->getType());
+ if (Result->getType() != RetTy)
+ Result = Builder.CreateTrunc(Result, RetTy);
+ return Result;
+ }
+
if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32)
return Builder.CreateFPTrunc(
Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index a0c62c2fc7775..1d8fe8c728f00 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -50,6 +50,15 @@ void __stlr16(unsigned __int16 volatile *, unsigned __int16);
void __stlr32(unsigned __int32 volatile *, unsigned __int32);
void __stlr64(unsigned __int64 volatile *, unsigned __int64);
+unsigned __int8 __cas8(unsigned __int8 volatile *, unsigned __int8,
+ unsigned __int8);
+unsigned __int16 __cas16(unsigned __int16 volatile *, unsigned __int16,
+ unsigned __int16);
+unsigned __int32 __cas32(unsigned __int32 volatile *, unsigned __int32,
+ unsigned __int32);
+unsigned __int64 __cas64(unsigned __int64 volatile *, unsigned __int64,
+ unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 6af7cd9adad24..797461d86803f 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -709,5 +709,61 @@ unsigned long long int check__ldapr64(unsigned long long int volatile *p) {
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__ldapr64'
+unsigned char test__cas8(unsigned char volatile* t, unsigned char c, unsigned char v)
+{
+ return __cas8 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__cas8(ptr{{.*}}%t, i8{{.*}}%c, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i8, ptr %c.addr, align 1
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i8 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.cas8(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__cas8'
+
+unsigned short test__cas16(unsigned short volatile* t, unsigned short c, unsigned short v)
+{
+ return __cas16 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__cas16(ptr{{.*}}%t, i16{{.*}}%c, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i16, ptr %c.addr, align 2
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i16 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.cas16(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__cas16'
+
+unsigned int test__cas32(unsigned int volatile* t, unsigned int c, unsigned int v)
+{
+ return __cas32 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__cas32(ptr{{.*}}%t, i32{{.*}}%c, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i32, ptr %c.addr, align 4
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.cas32(ptr %[[TMPT]], i32 %[[TMPC]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__cas32'
+
+unsigned long long int test__cas64(unsigned long long int volatile* t,
+ unsigned long long int c,
+ unsigned long long int v)
+{
+ return __cas64 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__cas64(ptr{{.*}}%t, i64{{.*}}%c, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i64, ptr %c.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.cas64(ptr %[[TMPT]], i64 %[[TMPC]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__cas64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 11a5fa4ef4011d4dded9e5363da984665d21f912 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 12:16:24 -0300
Subject: [PATCH 07/20] [aarch64] Add support for casa builtin
The new intrinsic issues CASA* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __casaX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 +++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 16 ++++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-cas.ll | 40 +++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 1e513520ea99e..7e9eb79f94fef 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -64,6 +64,21 @@ def int_aarch64_cas64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// CASA intrinsics — emit CASA* (acquire, no release) directly, regardless of
+// the LSE target feature. Same type conventions as cas*.
+def int_aarch64_casa8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casa16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casa32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casa64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 7fbcf20c64409..f5831e5392d3b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -594,6 +594,22 @@ def : Pat<(i32 (int_aarch64_cas32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
def : Pat<(i64 (int_aarch64_cas64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
(CASX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+// Unconditional patterns for the __casa* MSVC builtins (acquire ordering).
+def : Pat<(i32 (int_aarch64_casa8 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 255)), (and GPR32:$Rt, (i32 255)))),
+ (CASAB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casa8 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASAB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casa16 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 65535)), (and GPR32:$Rt, (i32 65535)))),
+ (CASAH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casa16 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASAH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casa32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASAW_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_casa64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
+ (CASAX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index c6cc76844b11d..dc777f13c4cd4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3035,6 +3035,7 @@ defm CASAL : CompareAndSwap<1, 1, "al">;
// Used by the __cas* MS intrinsics to force CAS* emission regardless of -march.
let isCodeGenOnly = 1 in {
defm CAS : CompareAndSwap_cg<0, 0, "">;
+ defm CASA : CompareAndSwap_cg<1, 0, "a">;
}
// v8.1 atomic CASP
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
index b3ee250bd96c3..99f1e5b50132f 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
@@ -47,4 +47,44 @@ define i64 @test_cas64(ptr %p, i64 %rs, i64 %rt) {
; CHECK-NEXT: ret
%r = call i64 @llvm.aarch64.cas64(ptr %p, i64 %rs, i64 %rt)
ret i64 %r
+}
+
+define i32 @test_casa8(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casa8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casab w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casa8(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casa16(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casa16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casah w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casa16(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casa32(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casa32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casa w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casa32(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i64 @test_casa64(ptr %p, i64 %rs, i64 %rt) {
+; CHECK-LABEL: test_casa64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casa x1, x2, [x0]
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.casa64(ptr %p, i64 %rs, i64 %rt)
+ ret i64 %r
}
\ No newline at end of file
>From 58e8e2339d94f403cf15b5615a9911580e00eb2a Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Wed, 15 Apr 2026 17:39:55 -0300
Subject: [PATCH 08/20] [aarch64] Add support for the __casa{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__casa8` - maps to CASAB.
* `__casa16` - maps to CASAH.
* `__casa32` - maps to CASA.
* `__casa64` - maps to CASA.
The emit is done using new intrisincs to issue CASA* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 ++++++-
clang/lib/Headers/arm64intr.h | 9 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 56 +++++++++++++++++++
4 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 8d1dd4aea6b03..b5f6699dd842c 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -422,4 +422,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __cas16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
def __cas32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
def __cas64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
+ def __casa8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char, unsigned char)">;
+ def __casa16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
+ def __casa32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
+ def __casa64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index bdcea53f508f1..a249199623b43 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5309,7 +5309,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
}
if (BuiltinID == AArch64::BI__cas8 || BuiltinID == AArch64::BI__cas16 ||
- BuiltinID == AArch64::BI__cas32 || BuiltinID == AArch64::BI__cas64) {
+ BuiltinID == AArch64::BI__cas32 || BuiltinID == AArch64::BI__cas64 ||
+ BuiltinID == AArch64::BI__casa8 || BuiltinID == AArch64::BI__casa16 ||
+ BuiltinID == AArch64::BI__casa32 || BuiltinID == AArch64::BI__casa64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5329,6 +5331,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_cas64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__casa8:
+ IntrID = Intrinsic::aarch64_casa8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casa16:
+ IntrID = Intrinsic::aarch64_casa16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casa32:
+ IntrID = Intrinsic::aarch64_casa32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casa64:
+ IntrID = Intrinsic::aarch64_casa64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 1d8fe8c728f00..1a133adf3d218 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -59,6 +59,15 @@ unsigned __int32 __cas32(unsigned __int32 volatile *, unsigned __int32,
unsigned __int64 __cas64(unsigned __int64 volatile *, unsigned __int64,
unsigned __int64);
+unsigned __int8 __casa8(unsigned __int8 volatile *, unsigned __int8,
+ unsigned __int8);
+unsigned __int16 __casa16(unsigned __int16 volatile *, unsigned __int16,
+ unsigned __int16);
+unsigned __int32 __casa32(unsigned __int32 volatile *, unsigned __int32,
+ unsigned __int32);
+unsigned __int64 __casa64(unsigned __int64 volatile *, unsigned __int64,
+ unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 797461d86803f..3c7aab6994ef6 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -765,5 +765,61 @@ unsigned long long int test__cas64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__cas64'
+unsigned char test__casa8(unsigned char volatile* t, unsigned char c, unsigned char v)
+{
+ return __casa8 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__casa8(ptr{{.*}}%t, i8{{.*}}%c, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i8, ptr %c.addr, align 1
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i8 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casa8(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casa8'
+
+unsigned short test__casa16(unsigned short volatile* t, unsigned short c, unsigned short v)
+{
+ return __casa16 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__casa16(ptr{{.*}}%t, i16{{.*}}%c, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i16, ptr %c.addr, align 2
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i16 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casa16(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casa16'
+
+unsigned int test__casa32(unsigned int volatile* t, unsigned int c, unsigned int v)
+{
+ return __casa32 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__casa32(ptr{{.*}}%t, i32{{.*}}%c, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i32, ptr %c.addr, align 4
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casa32(ptr %[[TMPT]], i32 %[[TMPC]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casa32'
+
+unsigned long long int test__casa64(unsigned long long int volatile* t,
+ unsigned long long int c,
+ unsigned long long int v)
+{
+ return __casa64 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__casa64(ptr{{.*}}%t, i64{{.*}}%c, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i64, ptr %c.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.casa64(ptr %[[TMPT]], i64 %[[TMPC]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casa64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From faea87e8ed34c069c20bac5bcf4f6a67b1c83736 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 13:06:36 -0300
Subject: [PATCH 09/20] [aarch64] Add support for casl builtin
The new intrinsic issues CASL* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __caslX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 +++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 16 +++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-cas.ll | 42 ++++++++++++++++++-
4 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 7e9eb79f94fef..947a231a29751 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -79,6 +79,21 @@ def int_aarch64_casa64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// CASL intrinsics — emit CASL* (release) directly, regardless of the LSE
+// target feature. Same type conventions as cas*.
+def int_aarch64_casl8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casl16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casl32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casl64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index f5831e5392d3b..22dc83bfc78d5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -610,6 +610,22 @@ def : Pat<(i32 (int_aarch64_casa32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
def : Pat<(i64 (int_aarch64_casa64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
(CASAX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+// Unconditional patterns for the __casl* MSVC builtins (release ordering).
+def : Pat<(i32 (int_aarch64_casl8 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 255)), (and GPR32:$Rt, (i32 255)))),
+ (CASLB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casl8 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASLB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casl16 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 65535)), (and GPR32:$Rt, (i32 65535)))),
+ (CASLH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casl16 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASLH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casl32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASLW_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_casl64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
+ (CASLX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index dc777f13c4cd4..4117a20abeedd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3036,6 +3036,7 @@ defm CASAL : CompareAndSwap<1, 1, "al">;
let isCodeGenOnly = 1 in {
defm CAS : CompareAndSwap_cg<0, 0, "">;
defm CASA : CompareAndSwap_cg<1, 0, "a">;
+ defm CASL : CompareAndSwap_cg<0, 1, "l">;
}
// v8.1 atomic CASP
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
index 99f1e5b50132f..717f23b8910f5 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
@@ -87,4 +87,44 @@ define i64 @test_casa64(ptr %p, i64 %rs, i64 %rt) {
; CHECK-NEXT: ret
%r = call i64 @llvm.aarch64.casa64(ptr %p, i64 %rs, i64 %rt)
ret i64 %r
-}
\ No newline at end of file
+}
+
+define i32 @test_casl8(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casl8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: caslb w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casl8(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casl16(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casl16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: caslh w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casl16(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casl32(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casl32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casl w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casl32(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i64 @test_casl64(ptr %p, i64 %rs, i64 %rt) {
+; CHECK-LABEL: test_casl64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casl x1, x2, [x0]
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.casl64(ptr %p, i64 %rs, i64 %rt)
+ ret i64 %r
+}
>From 0d96d4e941d884f5a7ca5568b463d5bc4696c65b Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 16 Apr 2026 09:15:28 -0300
Subject: [PATCH 10/20] [aarch64] Add support for the __casl{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__casl8` - maps to CASLB.
* `__casl16` - maps to CASLH.
* `__casl32` - maps to CASL.
* `__casl64` - maps to CASL.
The emit is done using new intrisincs to issue CASL* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 ++++++-
clang/lib/Headers/arm64intr.h | 9 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 56 +++++++++++++++++++
4 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index b5f6699dd842c..f547e5bed222d 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -426,4 +426,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __casa16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
def __casa32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
def __casa64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
+ def __casl8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char, unsigned char)">;
+ def __casl16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
+ def __casl32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
+ def __casl64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index a249199623b43..5502dd01efea0 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5311,7 +5311,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
if (BuiltinID == AArch64::BI__cas8 || BuiltinID == AArch64::BI__cas16 ||
BuiltinID == AArch64::BI__cas32 || BuiltinID == AArch64::BI__cas64 ||
BuiltinID == AArch64::BI__casa8 || BuiltinID == AArch64::BI__casa16 ||
- BuiltinID == AArch64::BI__casa32 || BuiltinID == AArch64::BI__casa64) {
+ BuiltinID == AArch64::BI__casa32 || BuiltinID == AArch64::BI__casa64 ||
+ BuiltinID == AArch64::BI__casl8 || BuiltinID == AArch64::BI__casl16 ||
+ BuiltinID == AArch64::BI__casl32 || BuiltinID == AArch64::BI__casl64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5347,6 +5349,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_casa64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__casl8:
+ IntrID = Intrinsic::aarch64_casl8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casl16:
+ IntrID = Intrinsic::aarch64_casl16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casl32:
+ IntrID = Intrinsic::aarch64_casl32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casl64:
+ IntrID = Intrinsic::aarch64_casl64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 1a133adf3d218..78da35fc3c26c 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -68,6 +68,15 @@ unsigned __int32 __casa32(unsigned __int32 volatile *, unsigned __int32,
unsigned __int64 __casa64(unsigned __int64 volatile *, unsigned __int64,
unsigned __int64);
+unsigned __int8 __casl8(unsigned __int8 volatile *, unsigned __int8,
+ unsigned __int8);
+unsigned __int16 __casl16(unsigned __int16 volatile *, unsigned __int16,
+ unsigned __int16);
+unsigned __int32 __casl32(unsigned __int32 volatile *, unsigned __int32,
+ unsigned __int32);
+unsigned __int64 __casl64(unsigned __int64 volatile *, unsigned __int64,
+ unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 3c7aab6994ef6..690828884c665 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -821,5 +821,61 @@ unsigned long long int test__casa64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__casa64'
+unsigned char test__casl8(unsigned char volatile* t, unsigned char c, unsigned char v)
+{
+ return __casl8 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__casl8(ptr{{.*}}%t, i8{{.*}}%c, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i8, ptr %c.addr, align 1
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i8 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casl8(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casl8'
+
+unsigned short test__casl16(unsigned short volatile* t, unsigned short c, unsigned short v)
+{
+ return __casl16 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__casl16(ptr{{.*}}%t, i16{{.*}}%c, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i16, ptr %c.addr, align 2
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i16 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casl16(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casl16'
+
+unsigned int test__casl32(unsigned int volatile* t, unsigned int c, unsigned int v)
+{
+ return __casl32 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__casl32(ptr{{.*}}%t, i32{{.*}}%c, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i32, ptr %c.addr, align 4
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casl32(ptr %[[TMPT]], i32 %[[TMPC]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casl32'
+
+unsigned long long int test__casl64(unsigned long long int volatile* t,
+ unsigned long long int c,
+ unsigned long long int v)
+{
+ return __casl64 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__casl64(ptr{{.*}}%t, i64{{.*}}%c, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i64, ptr %c.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.casl64(ptr %[[TMPT]], i64 %[[TMPC]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casl64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 16d9259c72eab3b0e8eca3b080bccaa17fa5c015 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 13:28:11 -0300
Subject: [PATCH 11/20] [aarch64] Add support for casal builtin
The new intrinsic issues CASAL* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __casalX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 +++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 16 ++++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-cas.ll | 40 +++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 947a231a29751..7ac2ee05289c6 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -94,6 +94,21 @@ def int_aarch64_casl64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// CASAL intrinsics — emit CASAL* (acquire/release) directly, regardless of the LSE
+// target feature. Same type conventions as cas*.
+def int_aarch64_casal8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casal16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casal32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_casal64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 22dc83bfc78d5..4dccba948999b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -626,6 +626,22 @@ def : Pat<(i32 (int_aarch64_casl32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
def : Pat<(i64 (int_aarch64_casl64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
(CASLX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+// Unconditional patterns for the __casal* MSVC builtins (acquire/release ordering).
+def : Pat<(i32 (int_aarch64_casal8 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 255)), (and GPR32:$Rt, (i32 255)))),
+ (CASALB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casal8 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASALB_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casal16 GPR64sp:$Rn,
+ (and GPR32:$Rs, (i32 65535)), (and GPR32:$Rt, (i32 65535)))),
+ (CASALH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casal16 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASALH_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_casal32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
+ (CASALW_cg GPR32:$Rs, GPR32:$Rt, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_casal64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
+ (CASALX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 4117a20abeedd..9ba8acc4f0d7e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3037,6 +3037,7 @@ let isCodeGenOnly = 1 in {
defm CAS : CompareAndSwap_cg<0, 0, "">;
defm CASA : CompareAndSwap_cg<1, 0, "a">;
defm CASL : CompareAndSwap_cg<0, 1, "l">;
+ defm CASAL : CompareAndSwap_cg<1, 1, "al">;
}
// v8.1 atomic CASP
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
index 717f23b8910f5..bb2d7ae508ed5 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-cas.ll
@@ -128,3 +128,43 @@ define i64 @test_casl64(ptr %p, i64 %rs, i64 %rt) {
%r = call i64 @llvm.aarch64.casl64(ptr %p, i64 %rs, i64 %rt)
ret i64 %r
}
+
+define i32 @test_casal8(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casal8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casalb w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casal8(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casal16(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casal16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casalh w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casal16(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i32 @test_casal32(ptr %p, i32 %rs, i32 %rt) {
+; CHECK-LABEL: test_casal32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casal w1, w2, [x0]
+; CHECK-NEXT: mov w0, w1
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.casal32(ptr %p, i32 %rs, i32 %rt)
+ ret i32 %r
+}
+
+define i64 @test_casal64(ptr %p, i64 %rs, i64 %rt) {
+; CHECK-LABEL: test_casal64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: casal x1, x2, [x0]
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.casal64(ptr %p, i64 %rs, i64 %rt)
+ ret i64 %r
+}
>From 98ce17e1ff29e410eb474692effd98415bf834f6 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 16 Apr 2026 10:47:20 -0300
Subject: [PATCH 12/20] [aarch64] Add support for the __casal{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__casal8` - maps to CASALB.
* `__casal16` - maps to CASALH.
* `__casal32` - maps to CASAL.
* `__casal64` - maps to CASAL.
The emit is done using new intrisincs to issue CASAL* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 ++++++-
clang/lib/Headers/arm64intr.h | 9 +++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 56 +++++++++++++++++++
4 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index f547e5bed222d..ba8a27811f600 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -430,4 +430,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __casl16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
def __casl32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
def __casl64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
+ def __casal8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char, unsigned char)">;
+ def __casal16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
+ def __casal32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
+ def __casal64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 5502dd01efea0..406aabc6295f0 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5313,7 +5313,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
BuiltinID == AArch64::BI__casa8 || BuiltinID == AArch64::BI__casa16 ||
BuiltinID == AArch64::BI__casa32 || BuiltinID == AArch64::BI__casa64 ||
BuiltinID == AArch64::BI__casl8 || BuiltinID == AArch64::BI__casl16 ||
- BuiltinID == AArch64::BI__casl32 || BuiltinID == AArch64::BI__casl64) {
+ BuiltinID == AArch64::BI__casl32 || BuiltinID == AArch64::BI__casl64 ||
+ BuiltinID == AArch64::BI__casal8 || BuiltinID == AArch64::BI__casal16 ||
+ BuiltinID == AArch64::BI__casal32 || BuiltinID == AArch64::BI__casal64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5365,6 +5367,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_casl64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__casal8:
+ IntrID = Intrinsic::aarch64_casal8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casal16:
+ IntrID = Intrinsic::aarch64_casal16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casal32:
+ IntrID = Intrinsic::aarch64_casal32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__casal64:
+ IntrID = Intrinsic::aarch64_casal64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 78da35fc3c26c..4f988f9de0a44 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -77,6 +77,15 @@ unsigned __int32 __casl32(unsigned __int32 volatile *, unsigned __int32,
unsigned __int64 __casl64(unsigned __int64 volatile *, unsigned __int64,
unsigned __int64);
+unsigned __int8 __casal8(unsigned __int8 volatile *, unsigned __int8,
+ unsigned __int8);
+unsigned __int16 __casal16(unsigned __int16 volatile *, unsigned __int16,
+ unsigned __int16);
+unsigned __int32 __casal32(unsigned __int32 volatile *, unsigned __int32,
+ unsigned __int32);
+unsigned __int64 __casal64(unsigned __int64 volatile *, unsigned __int64,
+ unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 690828884c665..b8f167e306cfa 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -877,5 +877,61 @@ unsigned long long int test__casl64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__casl64'
+unsigned char test__casal8(unsigned char volatile* t, unsigned char c, unsigned char v)
+{
+ return __casal8 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__casal8(ptr{{.*}}%t, i8{{.*}}%c, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i8, ptr %c.addr, align 1
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i8 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casal8(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casal8'
+
+unsigned short test__casal16(unsigned short volatile* t, unsigned short c, unsigned short v)
+{
+ return __casal16 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__casal16(ptr{{.*}}%t, i16{{.*}}%c, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i16, ptr %c.addr, align 2
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTC:[0-9]+]] = zext i16 %[[TMPC]] to i32
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casal16(ptr %[[TMPT]], i32 %[[ZEXTC]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[RETT:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[RETT]]
+// CHECK-LINUX: error: call to undeclared function '__casal16'
+
+unsigned int test__casal32(unsigned int volatile* t, unsigned int c, unsigned int v)
+{
+ return __casal32 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__casal32(ptr{{.*}}%t, i32{{.*}}%c, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i32, ptr %c.addr, align 4
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.casal32(ptr %[[TMPT]], i32 %[[TMPC]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casal32'
+
+unsigned long long int test__casal64(unsigned long long int volatile* t,
+ unsigned long long int c,
+ unsigned long long int v)
+{
+ return __casal64 (t, c, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__casal64(ptr{{.*}}%t, i64{{.*}}%c, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPC:[0-9]+]] = load i64, ptr %c.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.casal64(ptr %[[TMPT]], i64 %[[TMPC]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__casal64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 34db317b0fb7b18b678eed67d661aab3fba1c752 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 15:33:25 -0300
Subject: [PATCH 13/20] [aarch64] Add support for swp builtin
The new intrinsic issues SWP* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __swpX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 ++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 16 +++++++
.../lib/Target/AArch64/AArch64InstrFormats.td | 21 ++++++---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 +++
.../test/CodeGen/AArch64/ms-intrinsics-swp.ll | 46 +++++++++++++++++++
5 files changed, 98 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 7ac2ee05289c6..bc7fdbb012444 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -109,6 +109,21 @@ def int_aarch64_casal64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// SWP intrinsics — emit SWP* (no acquire/release) directly, regardless of the
+// LSE target feature. swp{b,h} value uses i32; swp64 uses i64.
+def int_aarch64_swp8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swp16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swp32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swp64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 4dccba948999b..1706f78075fd2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -642,6 +642,22 @@ def : Pat<(i32 (int_aarch64_casal32 GPR64sp:$Rn, GPR32:$Rs, GPR32:$Rt)),
def : Pat<(i64 (int_aarch64_casal64 GPR64sp:$Rn, GPR64:$Rs, GPR64:$Rt)),
(CASALX_cg GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn)>;
+// Unconditional patterns for the __swp* MSVC builtins (no ordering).
+// As with swp{b,h}, the zero-extension mask may survive or be eliminated by the
+// DAG combiner, so both masked and plain forms are needed.
+def : Pat<(i32 (int_aarch64_swp8 GPR64sp:$Rn, (and GPR32:$Rs, (i32 255)))),
+ (SWPB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swp8 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swp16 GPR64sp:$Rn, (and GPR32:$Rs, (i32 65535)))),
+ (SWPH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swp16 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swp32 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPW_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_swp64 GPR64sp:$Rn, GPR64:$Rs)),
+ (SWPX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index ae05efc43dec3..3e796a0e6738b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12511,16 +12511,25 @@ class BaseSWP<string order, string size, RegisterClass RC>
let Inst{11-10} = 0b00;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
- let Predicates = [HasLSE];
}
-multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
- let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseSWP<order, "b", GPR32>;
- let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseSWP<order, "h", GPR32>;
- let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseSWP<order, "", GPR32>;
- let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseSWP<order, "", GPR64>;
+multiclass Swap_impl<bits<1> Acq, bits<1> Rel, string order, list<Predicate> preds, string suffix> {
+ let Predicates = preds, Acq = Acq, Rel = Rel in {
+ let Sz = 0b00 in def "B" # suffix : BaseSWP<order, "b", GPR32>;
+ let Sz = 0b01 in def "H" # suffix : BaseSWP<order, "h", GPR32>;
+ let Sz = 0b10 in def "W" # suffix : BaseSWP<order, "", GPR32>;
+ let Sz = 0b11 in def "X" # suffix : BaseSWP<order, "", GPR64>;
+ }
}
+multiclass Swap<bits<1> Acq, bits<1> Rel, string order>
+ : Swap_impl<Acq, Rel, order, [HasLSE], "">;
+
+// Like Swap but without the HasLSE predicate — for isCodeGenOnly use by
+// MS intrinsics that must emit SWP* regardless of the -march setting.
+multiclass Swap_cg<bits<1> Acq, bits<1> Rel, string order>
+ : Swap_impl<Acq, Rel, order, [], "_cg">;
+
// v9.6a swap operations
class BaseSWPLSUI<string order, RegisterClass RC>
: I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swpt" # order,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 9ba8acc4f0d7e..65df5edbb2a03 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3066,6 +3066,12 @@ defm SWPA : Swap<1, 0, "a">;
defm SWPL : Swap<0, 1, "l">;
defm SWPAL : Swap<1, 1, "al">;
+// isCodeGenOnly=1: excluded from asm parser/disassembler, no HasLSE predicate.
+// Used by the __swp* MS intrinsics to force SWP* emission regardless of -march.
+let isCodeGenOnly = 1 in {
+ defm SWP : Swap_cg<0, 0, "">;
+}
+
// v9.6a atomic swap (FEAT_LSUI)
let Predicates = [HasLSUI] in {
defm SWPT : SwapLSUI<0, 0, "">;
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
new file mode 100644
index 0000000000000..f670a9157ba6d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-windows-msvc -fast-isel=0 -global-isel=false \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-windows-msvc -mattr=+lse -fast-isel=0 \
+; RUN: -global-isel=false -verify-machineinstrs < %s | FileCheck %s
+
+; Tests for the __swp* MS builtins on AArch64. These lower to
+; llvm.aarch64.swp* intrinsics and must select SWP* regardless of whether
+; +lse is present in the target features (the _cg ISel variants have no
+; feature predicate).
+
+define i32 @test_swp8(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swp8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpb w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swp8(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swp16(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swp16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swph w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swp16(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swp32(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swp32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swp w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swp32(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i64 @test_swp64(ptr %p, i64 %v) {
+; CHECK-LABEL: test_swp64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swp x1, x0, [x0]
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.swp64(ptr %p, i64 %v)
+ ret i64 %r
+}
\ No newline at end of file
>From 8ab525090aca310e8caf9d605273a7db942649b8 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Fri, 17 Apr 2026 10:05:23 -0300
Subject: [PATCH 14/20] [aarch64] Add support for the __swp{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__swp8` - maps to SWPB.
* `__swp16` - maps to SWPH.
* `__swp32` - maps to SWP.
* `__swp64` - maps to SWP.
The emit is done using new intrisincs to issue SWP* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 5 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 36 ++++++++++++++
clang/lib/Headers/arm64intr.h | 5 ++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 49 +++++++++++++++++++
4 files changed, 95 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index ba8a27811f600..80caec9f7ac05 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -434,4 +434,9 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __casal16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short, unsigned short)">;
def __casal32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int, unsigned int)">;
def __casal64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int, unsigned long long int)">;
+
+ def __swp8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char)">;
+ def __swp16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
+ def __swp32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
+ def __swp64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 406aabc6295f0..8d46ec362a53a 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5403,6 +5403,42 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Result;
}
+ if (BuiltinID == AArch64::BI__swp8 || BuiltinID == AArch64::BI__swp16 ||
+ BuiltinID == AArch64::BI__swp32 || BuiltinID == AArch64::BI__swp64) {
+ unsigned IntrID;
+ llvm::Type *IntrArgTy;
+ switch (BuiltinID) {
+ case AArch64::BI__swp8:
+ IntrID = Intrinsic::aarch64_swp8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swp16:
+ IntrID = Intrinsic::aarch64_swp16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swp32:
+ IntrID = Intrinsic::aarch64_swp32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swp64:
+ IntrID = Intrinsic::aarch64_swp64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
+ default:
+ llvm_unreachable("missing builtin ID in switch!");
+ }
+ Value *Ptr = EmitScalarExpr(E->getArg(0));
+ Value *Val = EmitScalarExpr(E->getArg(1));
+ if (Val->getType() != IntrArgTy)
+ Val = Builder.CreateZExt(Val, IntrArgTy);
+ Value *Result = Builder.CreateCall(CGM.getIntrinsic(IntrID), {Ptr, Val});
+ // SWP{B/H} return i32 (zero-extended); truncate to declared type.
+ llvm::Type *RetTy = ConvertType(E->getType());
+ if (Result->getType() != RetTy)
+ Result = Builder.CreateTrunc(Result, RetTy);
+ return Result;
+ }
+
if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32)
return Builder.CreateFPTrunc(
Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 4f988f9de0a44..eb19f84a1f6d0 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -86,6 +86,11 @@ unsigned __int32 __casal32(unsigned __int32 volatile *, unsigned __int32,
unsigned __int64 __casal64(unsigned __int64 volatile *, unsigned __int64,
unsigned __int64);
+unsigned __int8 __swp8(unsigned __int8 volatile *, unsigned __int8);
+unsigned __int16 __swp16(unsigned __int16 volatile *, unsigned __int16);
+unsigned __int32 __swp32(unsigned __int32 volatile *, unsigned __int32);
+unsigned __int64 __swp64(unsigned __int64 volatile *, unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index b8f167e306cfa..fabfd938c0009 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -933,5 +933,54 @@ unsigned long long int test__casal64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__casal64'
+unsigned char test__swp8(unsigned char volatile* t, unsigned char v)
+{
+ return __swp8(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__swp8(ptr{{.*}}%t, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swp8(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swp8'
+
+unsigned short test__swp16(unsigned short volatile* t, unsigned short v)
+{
+ return __swp16(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__swp16(ptr{{.*}}%t, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swp16(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swp16'
+
+unsigned int test__swp32(unsigned int volatile* t, unsigned int v)
+{
+ return __swp32(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__swp32(ptr{{.*}}%t, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swp32(ptr %[[TMPT]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swp32'
+
+unsigned long long int test__swp64(unsigned long long int volatile* t,
+ unsigned long long int v)
+{
+ return __swp64(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__swp64(ptr{{.*}}%t, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.swp64(ptr %[[TMPT]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swp64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 12885888252982884e8e11797af5af614a6c72dd Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 16:27:26 -0300
Subject: [PATCH 15/20] [aarch64] Add support for swpa builtin
The new intrinsic issues SWPA* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __swpaX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 14 +++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 13 +++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-swp.ll | 37 +++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index bc7fdbb012444..c8fbd9ecae2e9 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -124,6 +124,20 @@ def int_aarch64_swp64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// SWPA intrinsics — emit SWPA (acquire) directly, regardless of the LSE target
+def int_aarch64_swpa8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpa16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpa32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpa64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 1706f78075fd2..831b24d52ccc0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -658,6 +658,19 @@ def : Pat<(i32 (int_aarch64_swp32 GPR64sp:$Rn, GPR32:$Rs)),
def : Pat<(i64 (int_aarch64_swp64 GPR64sp:$Rn, GPR64:$Rs)),
(SWPX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpa8 GPR64sp:$Rn, (and GPR32:$Rs, (i32 255)))),
+ (SWPAB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpa8 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPAB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpa16 GPR64sp:$Rn, (and GPR32:$Rs, (i32 65535)))),
+ (SWPAH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpa16 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPAH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpa32 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPAW_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_swpa64 GPR64sp:$Rn, GPR64:$Rs)),
+ (SWPAX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 65df5edbb2a03..e8d2438867c3e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3070,6 +3070,7 @@ defm SWPAL : Swap<1, 1, "al">;
// Used by the __swp* MS intrinsics to force SWP* emission regardless of -march.
let isCodeGenOnly = 1 in {
defm SWP : Swap_cg<0, 0, "">;
+ defm SWPA : Swap_cg<1, 0, "a">;
}
// v9.6a atomic swap (FEAT_LSUI)
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
index f670a9157ba6d..d170a6d33218d 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
@@ -43,4 +43,41 @@ define i64 @test_swp64(ptr %p, i64 %v) {
; CHECK-NEXT: ret
%r = call i64 @llvm.aarch64.swp64(ptr %p, i64 %v)
ret i64 %r
+}
+
+
+define i32 @test_swpa8(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpa8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpab w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpa8(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpa16(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpa16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpah w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpa16(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpa32(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpa32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpa w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpa32(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i64 @test_swpa64(ptr %p, i64 %v) {
+; CHECK-LABEL: test_swpa64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpa x1, x0, [x0]
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.swpa64(ptr %p, i64 %v)
+ ret i64 %r
}
\ No newline at end of file
>From 7f90fb377dad3ddc9ec6ec11aca2bcdccb4e9966 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Fri, 17 Apr 2026 12:41:03 -0300
Subject: [PATCH 16/20] [aarch64] Add support for the __swpa{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__swpa8` - maps to SWPAB.
* `__swpa16` - maps to SWPAH.
* `__swpa32` - maps to SWPA.
* `__swpa64` - maps to SWPA.
The emit is done using new intrisincs to issue SWPA* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 +++++++-
clang/lib/Headers/arm64intr.h | 5 ++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 49 +++++++++++++++++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 80caec9f7ac05..3b57c8a826ea1 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -439,4 +439,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __swp16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
def __swp32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
def __swp64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
+ def __swpa8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char)">;
+ def __swpa16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
+ def __swpa32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
+ def __swpa64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 8d46ec362a53a..8587a18c6b0e9 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5404,7 +5404,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
}
if (BuiltinID == AArch64::BI__swp8 || BuiltinID == AArch64::BI__swp16 ||
- BuiltinID == AArch64::BI__swp32 || BuiltinID == AArch64::BI__swp64) {
+ BuiltinID == AArch64::BI__swp32 || BuiltinID == AArch64::BI__swp64 ||
+ BuiltinID == AArch64::BI__swpa8 || BuiltinID == AArch64::BI__swpa16 ||
+ BuiltinID == AArch64::BI__swpa32 || BuiltinID == AArch64::BI__swpa64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5424,6 +5426,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_swp64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__swpa8:
+ IntrID = Intrinsic::aarch64_swpa8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpa16:
+ IntrID = Intrinsic::aarch64_swpa16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpa32:
+ IntrID = Intrinsic::aarch64_swpa32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpa64:
+ IntrID = Intrinsic::aarch64_swpa64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index eb19f84a1f6d0..dd72fde0d6e89 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -91,6 +91,11 @@ unsigned __int16 __swp16(unsigned __int16 volatile *, unsigned __int16);
unsigned __int32 __swp32(unsigned __int32 volatile *, unsigned __int32);
unsigned __int64 __swp64(unsigned __int64 volatile *, unsigned __int64);
+unsigned __int8 __swpa8(unsigned __int8 volatile *, unsigned __int8);
+unsigned __int16 __swpa16(unsigned __int16 volatile *, unsigned __int16);
+unsigned __int32 __swpa32(unsigned __int32 volatile *, unsigned __int32);
+unsigned __int64 __swpa64(unsigned __int64 volatile *, unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index fabfd938c0009..5e3e0b6094835 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -982,5 +982,54 @@ unsigned long long int test__swp64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__swp64'
+unsigned char test__swpa8(unsigned char volatile* t, unsigned char v)
+{
+ return __swpa8(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__swpa8(ptr{{.*}}%t, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpa8(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpa8'
+
+unsigned short test__swpa16(unsigned short volatile* t, unsigned short v)
+{
+ return __swpa16(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__swpa16(ptr{{.*}}%t, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpa16(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpa16'
+
+unsigned int test__swpa32(unsigned int volatile* t, unsigned int v)
+{
+ return __swpa32(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__swpa32(ptr{{.*}}%t, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpa32(ptr %[[TMPT]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpa32'
+
+unsigned long long int test__swpa64(unsigned long long int volatile* t,
+ unsigned long long int v)
+{
+ return __swpa64(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__swpa64(ptr{{.*}}%t, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.swpa64(ptr %[[TMPT]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpa64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From a51300db2cd290801d6f8effb3739b57d496c19f Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 18:06:06 -0300
Subject: [PATCH 17/20] [aarch64] Add support for swpl builtin
The new intrinsic issues SWPL* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __swplX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 14 +++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 13 +++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-swp.ll | 38 ++++++++++++++++++-
4 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index c8fbd9ecae2e9..1cedde3256202 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -138,6 +138,20 @@ def int_aarch64_swpa64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// SWPL intrinsics — emit SWPL (release) directly, regardless of the LSE target
+def int_aarch64_swpl8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpl16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpl32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpl64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 831b24d52ccc0..86c8f4f8c1d2c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -671,6 +671,19 @@ def : Pat<(i32 (int_aarch64_swpa32 GPR64sp:$Rn, GPR32:$Rs)),
def : Pat<(i64 (int_aarch64_swpa64 GPR64sp:$Rn, GPR64:$Rs)),
(SWPAX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpl8 GPR64sp:$Rn, (and GPR32:$Rs, (i32 255)))),
+ (SWPLB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpl8 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPLB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpl16 GPR64sp:$Rn, (and GPR32:$Rs, (i32 65535)))),
+ (SWPLH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpl16 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPLH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpl32 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPLW_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_swpl64 GPR64sp:$Rn, GPR64:$Rs)),
+ (SWPLX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e8d2438867c3e..520a62fcda0a2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3071,6 +3071,7 @@ defm SWPAL : Swap<1, 1, "al">;
let isCodeGenOnly = 1 in {
defm SWP : Swap_cg<0, 0, "">;
defm SWPA : Swap_cg<1, 0, "a">;
+ defm SWPL : Swap_cg<0, 1, "l">;
}
// v9.6a atomic swap (FEAT_LSUI)
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
index d170a6d33218d..4275b1ced09b6 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
@@ -80,4 +80,40 @@ define i64 @test_swpa64(ptr %p, i64 %v) {
; CHECK-NEXT: ret
%r = call i64 @llvm.aarch64.swpa64(ptr %p, i64 %v)
ret i64 %r
-}
\ No newline at end of file
+}
+
+define i32 @test_swpl8(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpl8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swplb w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpl8(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpl16(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpl16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swplh w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpl16(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpl32(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpl32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpl w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpl32(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i64 @test_swpl64(ptr %p, i64 %v) {
+; CHECK-LABEL: test_swpl64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpl x1, x0, [x0]
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.swpl64(ptr %p, i64 %v)
+ ret i64 %r
+}
>From 191d7f6c126733f693a67b1cb6fd6ead68e139cc Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Fri, 17 Apr 2026 13:02:47 -0300
Subject: [PATCH 18/20] [aarch64] Add support for the __swpl{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__swpl8` - maps to SWPLB.
* `__swpl16` - maps to SWPLH.
* `__swpl32` - maps to SWPL.
* `__swpl64` - maps to SWPL.
The emit is done using new intrisincs to issue SWPL* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 +++++++-
clang/lib/Headers/arm64intr.h | 5 ++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 49 +++++++++++++++++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 3b57c8a826ea1..987fa1135147e 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -443,4 +443,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __swpa16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
def __swpa32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
def __swpa64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
+ def __swpl8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char)">;
+ def __swpl16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
+ def __swpl32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
+ def __swpl64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 8587a18c6b0e9..7b2edc0cef5e5 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5406,7 +5406,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
if (BuiltinID == AArch64::BI__swp8 || BuiltinID == AArch64::BI__swp16 ||
BuiltinID == AArch64::BI__swp32 || BuiltinID == AArch64::BI__swp64 ||
BuiltinID == AArch64::BI__swpa8 || BuiltinID == AArch64::BI__swpa16 ||
- BuiltinID == AArch64::BI__swpa32 || BuiltinID == AArch64::BI__swpa64) {
+ BuiltinID == AArch64::BI__swpa32 || BuiltinID == AArch64::BI__swpa64 ||
+ BuiltinID == AArch64::BI__swpl8 || BuiltinID == AArch64::BI__swpl16 ||
+ BuiltinID == AArch64::BI__swpl32 || BuiltinID == AArch64::BI__swpl64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5442,6 +5444,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_swpa64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__swpl8:
+ IntrID = Intrinsic::aarch64_swpl8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpl16:
+ IntrID = Intrinsic::aarch64_swpl16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpl32:
+ IntrID = Intrinsic::aarch64_swpl32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpl64:
+ IntrID = Intrinsic::aarch64_swpl64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index dd72fde0d6e89..1c7ab0b544b9c 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -96,6 +96,11 @@ unsigned __int16 __swpa16(unsigned __int16 volatile *, unsigned __int16);
unsigned __int32 __swpa32(unsigned __int32 volatile *, unsigned __int32);
unsigned __int64 __swpa64(unsigned __int64 volatile *, unsigned __int64);
+unsigned __int8 __swpl8(unsigned __int8 volatile *, unsigned __int8);
+unsigned __int16 __swpl16(unsigned __int16 volatile *, unsigned __int16);
+unsigned __int32 __swpl32(unsigned __int32 volatile *, unsigned __int32);
+unsigned __int64 __swpl64(unsigned __int64 volatile *, unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 5e3e0b6094835..34d8c675c4fcb 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -1031,5 +1031,54 @@ unsigned long long int test__swpa64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__swpa64'
+unsigned char test__swpl8(unsigned char volatile* t, unsigned char v)
+{
+ return __swpl8(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__swpl8(ptr{{.*}}%t, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpl8(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpl8'
+
+unsigned short test__swpl16(unsigned short volatile* t, unsigned short v)
+{
+ return __swpl16(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__swpl16(ptr{{.*}}%t, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpl16(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpl16'
+
+unsigned int test__swpl32(unsigned int volatile* t, unsigned int v)
+{
+ return __swpl32(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__swpl32(ptr{{.*}}%t, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpl32(ptr %[[TMPT]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpl32'
+
+unsigned long long int test__swpl64(unsigned long long int volatile* t,
+ unsigned long long int v)
+{
+ return __swpl64(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__swpl64(ptr{{.*}}%t, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.swpl64(ptr %[[TMPT]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpl64'
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
>From 96aa09f02c6eb359f93bb8369e3425b0407a4e0e Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Thu, 23 Apr 2026 18:23:55 -0300
Subject: [PATCH 19/20] [aarch64] Add support for swpal builtin
The new intrinsic issues SWPAL* instruction directly, regardless of LSE
target features. This will be used to implement MSVC __swpalX
builtins.
---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 15 ++++++++
.../lib/Target/AArch64/AArch64InstrAtomics.td | 13 +++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
.../test/CodeGen/AArch64/ms-intrinsics-swp.ll | 36 +++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 1cedde3256202..9af439a18ade4 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -152,6 +152,21 @@ def int_aarch64_swpl64 : Intrinsic<[llvm_i64_ty],
[llvm_ptr_ty, llvm_i64_ty],
[IntrNoFree, IntrWillReturn]>;
+// SWPAL intrinsics — emit SWPAL* (no acquire/release) directly, regardless of the
+// LSE target feature.
+def int_aarch64_swpal8 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpal16 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpal32 : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoFree, IntrWillReturn]>;
+def int_aarch64_swpal64 : Intrinsic<[llvm_i64_ty],
+ [llvm_ptr_ty, llvm_i64_ty],
+ [IntrNoFree, IntrWillReturn]>;
+
def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 86c8f4f8c1d2c..79a988d63366b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -684,6 +684,19 @@ def : Pat<(i32 (int_aarch64_swpl32 GPR64sp:$Rn, GPR32:$Rs)),
def : Pat<(i64 (int_aarch64_swpl64 GPR64sp:$Rn, GPR64:$Rs)),
(SWPLX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpal8 GPR64sp:$Rn, (and GPR32:$Rs, (i32 255)))),
+ (SWPALB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpal8 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPALB_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpal16 GPR64sp:$Rn, (and GPR32:$Rs, (i32 65535)))),
+ (SWPALH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpal16 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPALH_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i32 (int_aarch64_swpal32 GPR64sp:$Rn, GPR32:$Rs)),
+ (SWPALW_cg GPR32:$Rs, GPR64sp:$Rn)>;
+def : Pat<(i64 (int_aarch64_swpal64 GPR64sp:$Rn, GPR64:$Rs)),
+ (SWPALX_cg GPR64:$Rs, GPR64sp:$Rn)>;
+
// v8.9a/v9.4a FEAT_LRCPC patterns
let Predicates = [HasRCPC3, HasNEON] in {
// LDAP1 loads
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 520a62fcda0a2..4379cde14354d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3072,6 +3072,7 @@ let isCodeGenOnly = 1 in {
defm SWP : Swap_cg<0, 0, "">;
defm SWPA : Swap_cg<1, 0, "a">;
defm SWPL : Swap_cg<0, 1, "l">;
+ defm SWPAL : Swap_cg<1, 1, "al">;
}
// v9.6a atomic swap (FEAT_LSUI)
diff --git a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
index 4275b1ced09b6..c01fee0c9e1ff 100644
--- a/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
+++ b/llvm/test/CodeGen/AArch64/ms-intrinsics-swp.ll
@@ -117,3 +117,39 @@ define i64 @test_swpl64(ptr %p, i64 %v) {
%r = call i64 @llvm.aarch64.swpl64(ptr %p, i64 %v)
ret i64 %r
}
+
+define i32 @test_swpal8(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpal8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpalb w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpal8(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpal16(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpal16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpalh w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpal16(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i32 @test_swpal32(ptr %p, i32 %v) {
+; CHECK-LABEL: test_swpal32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpal w1, w0, [x0]
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.aarch64.swpal32(ptr %p, i32 %v)
+ ret i32 %r
+}
+
+define i64 @test_swpal64(ptr %p, i64 %v) {
+; CHECK-LABEL: test_swpal64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: swpal x1, x0, [x0]
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.aarch64.swpal64(ptr %p, i64 %v)
+ ret i64 %r
+}
>From 4a144e776342b8fccf7937b0e86e44c8ce206261 Mon Sep 17 00:00:00 2001
From: Adhemerval Zanella <zatrazz at gmail.com>
Date: Fri, 17 Apr 2026 13:20:15 -0300
Subject: [PATCH 20/20] [aarch64] Add support for the __swpal{8|16|32|64} MS
intrinsics
Adds support for the following MSVC intrinsics:
* `__swpal8` - maps to SWPALB.
* `__swpal16` - maps to SWPALH.
* `__swpal32` - maps to SWPAL.
* `__swpal64` - maps to SWPAL.
The emit is done using new intrisincs to issue SWPAL* instruction
directly, regardless of LSE target feature. This mimics MSVC compiler
and the idea of the builtin to mimic an inline asm.
These are documented at:
<https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180>
---
clang/include/clang/Basic/BuiltinsAArch64.td | 4 ++
clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 20 +++++++-
clang/lib/Headers/arm64intr.h | 5 ++
.../test/CodeGen/arm64-microsoft-intrinsics.c | 50 +++++++++++++++++++
4 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td
index 987fa1135147e..0177c8b0aa8fb 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.td
+++ b/clang/include/clang/Basic/BuiltinsAArch64.td
@@ -447,4 +447,8 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES",
def __swpl16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
def __swpl32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
def __swpl64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
+ def __swpal8 : AArch64NoPrefixTargetLibBuiltin<"unsigned char (unsigned char volatile *, unsigned char)">;
+ def __swpal16 : AArch64NoPrefixTargetLibBuiltin<"unsigned short (unsigned short volatile *, unsigned short)">;
+ def __swpal32 : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int volatile *, unsigned int)">;
+ def __swpal64 : AArch64NoPrefixTargetLibBuiltin<"unsigned long long int (unsigned long long int volatile *, unsigned long long int)">;
}
diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 7b2edc0cef5e5..74eba496b18aa 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -5408,7 +5408,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
BuiltinID == AArch64::BI__swpa8 || BuiltinID == AArch64::BI__swpa16 ||
BuiltinID == AArch64::BI__swpa32 || BuiltinID == AArch64::BI__swpa64 ||
BuiltinID == AArch64::BI__swpl8 || BuiltinID == AArch64::BI__swpl16 ||
- BuiltinID == AArch64::BI__swpl32 || BuiltinID == AArch64::BI__swpl64) {
+ BuiltinID == AArch64::BI__swpl32 || BuiltinID == AArch64::BI__swpl64 ||
+ BuiltinID == AArch64::BI__swpal8 || BuiltinID == AArch64::BI__swpal16 ||
+ BuiltinID == AArch64::BI__swpal32 || BuiltinID == AArch64::BI__swpal64) {
unsigned IntrID;
llvm::Type *IntrArgTy;
switch (BuiltinID) {
@@ -5460,6 +5462,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
IntrID = Intrinsic::aarch64_swpl64;
IntrArgTy = Builder.getInt64Ty();
break;
+ case AArch64::BI__swpal8:
+ IntrID = Intrinsic::aarch64_swpal8;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpal16:
+ IntrID = Intrinsic::aarch64_swpal16;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpal32:
+ IntrID = Intrinsic::aarch64_swpal32;
+ IntrArgTy = Builder.getInt32Ty();
+ break;
+ case AArch64::BI__swpal64:
+ IntrID = Intrinsic::aarch64_swpal64;
+ IntrArgTy = Builder.getInt64Ty();
+ break;
default:
llvm_unreachable("missing builtin ID in switch!");
}
diff --git a/clang/lib/Headers/arm64intr.h b/clang/lib/Headers/arm64intr.h
index 1c7ab0b544b9c..58945148bea7b 100644
--- a/clang/lib/Headers/arm64intr.h
+++ b/clang/lib/Headers/arm64intr.h
@@ -101,6 +101,11 @@ unsigned __int16 __swpl16(unsigned __int16 volatile *, unsigned __int16);
unsigned __int32 __swpl32(unsigned __int32 volatile *, unsigned __int32);
unsigned __int64 __swpl64(unsigned __int64 volatile *, unsigned __int64);
+unsigned __int8 __swpal8(unsigned __int8 volatile *, unsigned __int8);
+unsigned __int16 __swpal16(unsigned __int16 volatile *, unsigned __int16);
+unsigned __int32 __swpal32(unsigned __int32 volatile *, unsigned __int32);
+unsigned __int64 __swpal64(unsigned __int64 volatile *, unsigned __int64);
+
#ifdef __cplusplus
}
#endif
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 34d8c675c4fcb..145ce2b984dbd 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -1080,5 +1080,55 @@ unsigned long long int test__swpl64(unsigned long long int volatile* t,
// CHECK-MSCOMPAT: ret i64 %[[RET]]
// CHECK-LINUX: error: call to undeclared function '__swpl64'
+unsigned char test__swpal8(unsigned char volatile* t, unsigned char v)
+{
+ return __swpal8(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i8 @test__swpal8(ptr{{.*}}%t, i8{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i8, ptr %v.addr, align 1
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i8 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpal8(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i8
+// CHECK-MSCOMPAT: ret i8 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpal8'
+
+unsigned short test__swpal16(unsigned short volatile* t, unsigned short v)
+{
+ return __swpal16(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i16 @test__swpal16(ptr{{.*}}%t, i16{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i16, ptr %v.addr, align 2
+// CHECK-MSCOMPAT: %[[ZEXTV:[0-9]+]] = zext i16 %[[TMPV]] to i32
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpal16(ptr %[[TMPT]], i32 %[[ZEXTV]])
+// CHECK-MSCOMPAT: %[[TRUNC:[0-9]+]] = trunc i32 %[[RET]] to i16
+// CHECK-MSCOMPAT: ret i16 %[[TRUNC]]
+// CHECK-LINUX: error: call to undeclared function '__swpal16'
+
+unsigned int test__swpal32(unsigned int volatile* t, unsigned int v)
+{
+ return __swpal32(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i32 @test__swpal32(ptr{{.*}}%t, i32{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i32, ptr %v.addr, align 4
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i32 @llvm.aarch64.swpal32(ptr %[[TMPT]], i32 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i32 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpal32'
+
+unsigned long long int test__swpal64(unsigned long long int volatile* t,
+ unsigned long long int v)
+{
+ return __swpal64(t, v);
+}
+// CHECK-MSCOMPAT-LABEL: define{{.*}}i64 @test__swpal64(ptr{{.*}}%t, i64{{.*}}%v){{.*}}{
+// CHECK-MSCOMPAT: %[[TMPT:[0-9]+]] = load ptr, ptr %t.addr, align 8
+// CHECK-MSCOMPAT: %[[TMPV:[0-9]+]] = load i64, ptr %v.addr, align 8
+// CHECK-MSCOMPAT: %[[RET:[0-9]+]] = call i64 @llvm.aarch64.swpal64(ptr %[[TMPT]], i64 %[[TMPV]])
+// CHECK-MSCOMPAT: ret i64 %[[RET]]
+// CHECK-LINUX: error: call to undeclared function '__swpal64'
+
+
// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}
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