[clang] [CIR] Add floating-point type descriptors to decodeFixedType (PR #194483)

via cfe-commits cfe-commits at lists.llvm.org
Mon Apr 27 15:50:42 PDT 2026


https://github.com/adams381 created https://github.com/llvm/llvm-project/pull/194483

`decodeFixedType` in `CIRGenBuiltin.cpp` only handled `Void`, `Integer`, `Vector`, and `Pointer` IIT descriptor kinds.  Any target builtin whose intrinsic signature includes a floating-point type (e.g. `__builtin_ia32_rsqrtps` → `<4 x float>`) hit the default `errorNYI` path, which returned `VoidType`.  `VectorType::get(VoidType, N)` then tripped the MLIR type verifier assertion.

Adds `Half`, `BFloat`, `Float`, `Double`, and `Quad` cases.

Found while building the Eigen test suite with CIR — this was crashing 21 of 135 test files.


>From 25659a381c87ac85882e375646102d18c0352c16 Mon Sep 17 00:00:00 2001
From: Adam Smith <adams at nvidia.com>
Date: Mon, 27 Apr 2026 15:49:24 -0700
Subject: [PATCH] [CIR] Add floating-point type descriptors to decodeFixedType

The decodeFixedType function in CIRGenBuiltin.cpp was missing
cases for Half, BFloat, Float, Double, and Quad intrinsic type
descriptors.  When a target builtin used floating-point vector
types (e.g., __builtin_ia32_rsqrtps with <4 x float>), the
function fell through to the default NYI path and returned
VoidType.  This caused VectorType::get(VoidType, N) to trigger
a StorageUniquerSupport assertion failure.

Add the five missing cases mapping to cir::FP16Type,
cir::BF16Type, cir::SingleType, cir::DoubleType, and
cir::FP128Type.  Add regression tests for rsqrtps and rcpps
builtins that exercise the Float descriptor path.

Made-with: Cursor
---
 clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp | 10 ++++++++++
 clang/test/CIR/CodeGen/builtins-x86.c   | 24 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
index 589833c0971b8..9a3493a3bd1e5 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
@@ -860,6 +860,16 @@ decodeFixedType(CIRGenFunction &cgf,
   switch (descriptor.Kind) {
   case IITDescriptor::Void:
     return cir::VoidType::get(context);
+  case IITDescriptor::Half:
+    return cir::FP16Type::get(context);
+  case IITDescriptor::BFloat:
+    return cir::BF16Type::get(context);
+  case IITDescriptor::Float:
+    return cir::SingleType::get(context);
+  case IITDescriptor::Double:
+    return cir::DoubleType::get(context);
+  case IITDescriptor::Quad:
+    return cir::FP128Type::get(context);
   // If the intrinsic expects unsigned integers, the signedness is corrected in
   // correctIntegerSignedness()
   case IITDescriptor::Integer:
diff --git a/clang/test/CIR/CodeGen/builtins-x86.c b/clang/test/CIR/CodeGen/builtins-x86.c
index 8511286a79723..eab3f61b25562 100644
--- a/clang/test/CIR/CodeGen/builtins-x86.c
+++ b/clang/test/CIR/CodeGen/builtins-x86.c
@@ -56,6 +56,30 @@ void test_clflush(void* a){
 typedef float v4f __attribute__((vector_size(16)));
 typedef int   v4i __attribute__((vector_size(16)));
 
+v4f test_rsqrtps(v4f a) {
+  // CIR-LABEL: @test_rsqrtps
+  // CIR: cir.call_llvm_intrinsic "x86.sse.rsqrt.ps" {{.*}} : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
+
+  // LLVM-LABEL: @test_rsqrtps
+  // LLVM: call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> {{.*}})
+
+  // OGCG-LABEL: @test_rsqrtps
+  // OGCG: call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> {{.*}})
+  return __builtin_ia32_rsqrtps(a);
+}
+
+v4f test_rcpps(v4f a) {
+  // CIR-LABEL: @test_rcpps
+  // CIR: cir.call_llvm_intrinsic "x86.sse.rcp.ps" {{.*}} : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
+
+  // LLVM-LABEL: @test_rcpps
+  // LLVM: call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> {{.*}})
+
+  // OGCG-LABEL: @test_rcpps
+  // OGCG: call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> {{.*}})
+  return __builtin_ia32_rcpps(a);
+}
+
 v4i test_convertvector(v4f a) {
   // CIR-LABEL: test_convertvector
   // CIR: cir.cast float_to_int %{{.*}} : !cir.vector<4 x !cir.float> -> !cir.vector<4 x !s32i>



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