[clang] [CIR][AArch64] Upstream addition-across-vector (incl. widening) NEON builtins (PR #193396)

[Andrzej Warzyński via cfe-commits]

https://github.com/banach-space commented:

The implementation makes sense to me, thank you. Overall this is quite neat!

I like how you compressed these cases together:
```cpp
  case NEON::BI__builtin_neon_vaddlv_u8:
  case NEON::BI__builtin_neon_vaddlv_u16:
  case NEON::BI__builtin_neon_vaddlvq_u8:
  case NEON::BI__builtin_neon_vaddlvq_u16:
  case NEON::BI__builtin_neon_vaddlv_s8:
  case NEON::BI__builtin_neon_vaddlv_s16:
  case NEON::BI__builtin_neon_vaddlvq_s8:
  case NEON::BI__builtin_neon_vaddlvq_s16:
```

Would you be OK to do the same in the original implementation in https://github.com/llvm/llvm-project/blob/main/clang/lib/CodeGen/TargetBuiltins/ARM.cpp? IIUC, the IR won't change and we will be making sure that both implementations benefit from your eye for improvements :) I will happily accept that and don't expect any push back from other reviewers.

Thanks you!

https://github.com/llvm/llvm-project/pull/193396