[clang] 8a8d26f - [RISCV] Support reinterpret cast intrinisc for OFP8 (#191626)
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cfe-commits at lists.llvm.org
Mon Apr 27 03:03:56 PDT 2026
Author: Brandon Wu
Date: 2026-04-27T10:03:51Z
New Revision: 8a8d26fe77dc76864aa86171a4bcf0c645b16013
URL: https://github.com/llvm/llvm-project/commit/8a8d26fe77dc76864aa86171a4bcf0c645b16013
DIFF: https://github.com/llvm/llvm-project/commit/8a8d26fe77dc76864aa86171a4bcf0c645b16013.diff
LOG: [RISCV] Support reinterpret cast intrinisc for OFP8 (#191626)
spec: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/433
stacked on: https://github.com/llvm/llvm-project/pull/191349
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
Modified:
clang/include/clang/Basic/riscv_vector.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 414769e2429cc..06b13dd5725f8 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1805,6 +1805,12 @@ let HasMasked = false, HasVL = false, IRName = "" in {
def vreinterpret_u_bf16 : RVVBuiltin<"vUv", "Uvv", "y", "Uv">;
def vreinterpret_bf16_i : RVVBuiltin<"Ivv", "vIv", "y", "v">;
def vreinterpret_bf16_u : RVVBuiltin<"Uvv", "vUv", "y", "v">;
+ let RequiredFeatures = ["zvfofp8min"] in {
+ def vreinterpret_u_f8e4m3 : RVVBuiltin<"vUv", "Uvv", "a", "Uv">;
+ def vreinterpret_f8e4m3_u : RVVBuiltin<"Uvv", "vUv", "a", "v">;
+ def vreinterpret_u_f8e5m2 : RVVBuiltin<"vUv", "Uvv", "b", "Uv">;
+ def vreinterpret_f8e5m2_u : RVVBuiltin<"Uvv", "vUv", "b", "v">;
+ }
// Reinterpret between
diff erent SEW under the same LMUL
foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)",
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
new file mode 100644
index 0000000000000..0a11e9eb14476
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
@@ -0,0 +1,260 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfbfmin \
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vfloat8e4m3mf8_t test_vreinterpret_v_u8mf8_f8e4m3mf8(vuint8mf8_t src) {
+ return __riscv_vreinterpret_v_u8mf8_f8e4m3mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vfloat8e4m3mf4_t test_vreinterpret_v_u8mf4_f8e4m3mf4(vuint8mf4_t src) {
+ return __riscv_vreinterpret_v_u8mf4_f8e4m3mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vfloat8e4m3mf2_t test_vreinterpret_v_u8mf2_f8e4m3mf2(vuint8mf2_t src) {
+ return __riscv_vreinterpret_v_u8mf2_f8e4m3mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vfloat8e4m3m1_t test_vreinterpret_v_u8m1_f8e4m3m1(vuint8m1_t src) {
+ return __riscv_vreinterpret_v_u8m1_f8e4m3m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vfloat8e4m3m2_t test_vreinterpret_v_u8m2_f8e4m3m2(vuint8m2_t src) {
+ return __riscv_vreinterpret_v_u8m2_f8e4m3m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vfloat8e4m3m4_t test_vreinterpret_v_u8m4_f8e4m3m4(vuint8m4_t src) {
+ return __riscv_vreinterpret_v_u8m4_f8e4m3m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vfloat8e4m3m8_t test_vreinterpret_v_u8m8_f8e4m3m8(vuint8m8_t src) {
+ return __riscv_vreinterpret_v_u8m8_f8e4m3m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vuint8mf8_t test_vreinterpret_v_f8e4m3mf8_u8mf8(vfloat8e4m3mf8_t src) {
+ return __riscv_vreinterpret_v_f8e4m3mf8_u8mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vuint8mf4_t test_vreinterpret_v_f8e4m3mf4_u8mf4(vfloat8e4m3mf4_t src) {
+ return __riscv_vreinterpret_v_f8e4m3mf4_u8mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vuint8mf2_t test_vreinterpret_v_f8e4m3mf2_u8mf2(vfloat8e4m3mf2_t src) {
+ return __riscv_vreinterpret_v_f8e4m3mf2_u8mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vuint8m1_t test_vreinterpret_v_f8e4m3m1_u8m1(vfloat8e4m3m1_t src) {
+ return __riscv_vreinterpret_v_f8e4m3m1_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vuint8m2_t test_vreinterpret_v_f8e4m3m2_u8m2(vfloat8e4m3m2_t src) {
+ return __riscv_vreinterpret_v_f8e4m3m2_u8m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vuint8m4_t test_vreinterpret_v_f8e4m3m4_u8m4(vfloat8e4m3m4_t src) {
+ return __riscv_vreinterpret_v_f8e4m3m4_u8m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vuint8m8_t test_vreinterpret_v_f8e4m3m8_u8m8(vfloat8e4m3m8_t src) {
+ return __riscv_vreinterpret_v_f8e4m3m8_u8m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vfloat8e5m2mf8_t test_vreinterpret_v_u8mf8_f8e5m2mf8(vuint8mf8_t src) {
+ return __riscv_vreinterpret_v_u8mf8_f8e5m2mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vfloat8e5m2mf4_t test_vreinterpret_v_u8mf4_f8e5m2mf4(vuint8mf4_t src) {
+ return __riscv_vreinterpret_v_u8mf4_f8e5m2mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vfloat8e5m2mf2_t test_vreinterpret_v_u8mf2_f8e5m2mf2(vuint8mf2_t src) {
+ return __riscv_vreinterpret_v_u8mf2_f8e5m2mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vfloat8e5m2m1_t test_vreinterpret_v_u8m1_f8e5m2m1(vuint8m1_t src) {
+ return __riscv_vreinterpret_v_u8m1_f8e5m2m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vfloat8e5m2m2_t test_vreinterpret_v_u8m2_f8e5m2m2(vuint8m2_t src) {
+ return __riscv_vreinterpret_v_u8m2_f8e5m2m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vfloat8e5m2m4_t test_vreinterpret_v_u8m4_f8e5m2m4(vuint8m4_t src) {
+ return __riscv_vreinterpret_v_u8m4_f8e5m2m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vfloat8e5m2m8_t test_vreinterpret_v_u8m8_f8e5m2m8(vuint8m8_t src) {
+ return __riscv_vreinterpret_v_u8m8_f8e5m2m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vuint8mf8_t test_vreinterpret_v_f8e5m2mf8_u8mf8(vfloat8e5m2mf8_t src) {
+ return __riscv_vreinterpret_v_f8e5m2mf8_u8mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vuint8mf4_t test_vreinterpret_v_f8e5m2mf4_u8mf4(vfloat8e5m2mf4_t src) {
+ return __riscv_vreinterpret_v_f8e5m2mf4_u8mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vuint8mf2_t test_vreinterpret_v_f8e5m2mf2_u8mf2(vfloat8e5m2mf2_t src) {
+ return __riscv_vreinterpret_v_f8e5m2mf2_u8mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vuint8m1_t test_vreinterpret_v_f8e5m2m1_u8m1(vfloat8e5m2m1_t src) {
+ return __riscv_vreinterpret_v_f8e5m2m1_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vuint8m2_t test_vreinterpret_v_f8e5m2m2_u8m2(vfloat8e5m2m2_t src) {
+ return __riscv_vreinterpret_v_f8e5m2m2_u8m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vuint8m4_t test_vreinterpret_v_f8e5m2m4_u8m4(vfloat8e5m2m4_t src) {
+ return __riscv_vreinterpret_v_f8e5m2m4_u8m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vuint8m8_t test_vreinterpret_v_f8e5m2m8_u8m8(vfloat8e5m2m8_t src) {
+ return __riscv_vreinterpret_v_f8e5m2m8_u8m8(src);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
new file mode 100644
index 0000000000000..c5a7ee0b6564c
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
@@ -0,0 +1,260 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfbfmin \
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vfloat8e4m3mf8_t test_vreinterpret_v_u8mf8_f8e4m3mf8(vuint8mf8_t src) {
+ return __riscv_vreinterpret_f8e4m3mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vfloat8e4m3mf4_t test_vreinterpret_v_u8mf4_f8e4m3mf4(vuint8mf4_t src) {
+ return __riscv_vreinterpret_f8e4m3mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vfloat8e4m3mf2_t test_vreinterpret_v_u8mf2_f8e4m3mf2(vuint8mf2_t src) {
+ return __riscv_vreinterpret_f8e4m3mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vfloat8e4m3m1_t test_vreinterpret_v_u8m1_f8e4m3m1(vuint8m1_t src) {
+ return __riscv_vreinterpret_f8e4m3m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vfloat8e4m3m2_t test_vreinterpret_v_u8m2_f8e4m3m2(vuint8m2_t src) {
+ return __riscv_vreinterpret_f8e4m3m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vfloat8e4m3m4_t test_vreinterpret_v_u8m4_f8e4m3m4(vuint8m4_t src) {
+ return __riscv_vreinterpret_f8e4m3m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vfloat8e4m3m8_t test_vreinterpret_v_u8m8_f8e4m3m8(vuint8m8_t src) {
+ return __riscv_vreinterpret_f8e4m3m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vuint8mf8_t test_vreinterpret_v_f8e4m3mf8_u8mf8(vfloat8e4m3mf8_t src) {
+ return __riscv_vreinterpret_u8mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vuint8mf4_t test_vreinterpret_v_f8e4m3mf4_u8mf4(vfloat8e4m3mf4_t src) {
+ return __riscv_vreinterpret_u8mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vuint8mf2_t test_vreinterpret_v_f8e4m3mf2_u8mf2(vfloat8e4m3mf2_t src) {
+ return __riscv_vreinterpret_u8mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vuint8m1_t test_vreinterpret_v_f8e4m3m1_u8m1(vfloat8e4m3m1_t src) {
+ return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vuint8m2_t test_vreinterpret_v_f8e4m3m2_u8m2(vfloat8e4m3m2_t src) {
+ return __riscv_vreinterpret_u8m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vuint8m4_t test_vreinterpret_v_f8e4m3m4_u8m4(vfloat8e4m3m4_t src) {
+ return __riscv_vreinterpret_u8m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vuint8m8_t test_vreinterpret_v_f8e4m3m8_u8m8(vfloat8e4m3m8_t src) {
+ return __riscv_vreinterpret_u8m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vfloat8e5m2mf8_t test_vreinterpret_v_u8mf8_f8e5m2mf8(vuint8mf8_t src) {
+ return __riscv_vreinterpret_f8e5m2mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vfloat8e5m2mf4_t test_vreinterpret_v_u8mf4_f8e5m2mf4(vuint8mf4_t src) {
+ return __riscv_vreinterpret_f8e5m2mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vfloat8e5m2mf2_t test_vreinterpret_v_u8mf2_f8e5m2mf2(vuint8mf2_t src) {
+ return __riscv_vreinterpret_f8e5m2mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vfloat8e5m2m1_t test_vreinterpret_v_u8m1_f8e5m2m1(vuint8m1_t src) {
+ return __riscv_vreinterpret_f8e5m2m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vfloat8e5m2m2_t test_vreinterpret_v_u8m2_f8e5m2m2(vuint8m2_t src) {
+ return __riscv_vreinterpret_f8e5m2m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vfloat8e5m2m4_t test_vreinterpret_v_u8m4_f8e5m2m4(vuint8m4_t src) {
+ return __riscv_vreinterpret_f8e5m2m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vfloat8e5m2m8_t test_vreinterpret_v_u8m8_f8e5m2m8(vuint8m8_t src) {
+ return __riscv_vreinterpret_f8e5m2m8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(
+// CHECK-RV64-SAME: <vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]
+//
+vuint8mf8_t test_vreinterpret_v_f8e5m2mf8_u8mf8(vfloat8e5m2mf8_t src) {
+ return __riscv_vreinterpret_u8mf8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(
+// CHECK-RV64-SAME: <vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]
+//
+vuint8mf4_t test_vreinterpret_v_f8e5m2mf4_u8mf4(vfloat8e5m2mf4_t src) {
+ return __riscv_vreinterpret_u8mf4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(
+// CHECK-RV64-SAME: <vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]
+//
+vuint8mf2_t test_vreinterpret_v_f8e5m2mf2_u8mf2(vfloat8e5m2mf2_t src) {
+ return __riscv_vreinterpret_u8mf2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(
+// CHECK-RV64-SAME: <vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]
+//
+vuint8m1_t test_vreinterpret_v_f8e5m2m1_u8m1(vfloat8e5m2m1_t src) {
+ return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(
+// CHECK-RV64-SAME: <vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]
+//
+vuint8m2_t test_vreinterpret_v_f8e5m2m2_u8m2(vfloat8e5m2m2_t src) {
+ return __riscv_vreinterpret_u8m2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(
+// CHECK-RV64-SAME: <vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]
+//
+vuint8m4_t test_vreinterpret_v_f8e5m2m4_u8m4(vfloat8e5m2m4_t src) {
+ return __riscv_vreinterpret_u8m4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(
+// CHECK-RV64-SAME: <vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: [[ENTRY:.*:]]
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]
+//
+vuint8m8_t test_vreinterpret_v_f8e5m2m8_u8m8(vfloat8e5m2m8_t src) {
+ return __riscv_vreinterpret_u8m8(src);
+}
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