[clang] [clang][CIR] Add lowering for vrshr_ and vrshrq_ rounding intrinsics (PR #194229)
Andrzej Warzyński via cfe-commits
cfe-commits at lists.llvm.org
Sun Apr 26 04:37:00 PDT 2026
https://github.com/banach-space created https://github.com/llvm/llvm-project/pull/194229
This PR adds lowering for the vector rounding shift right intrinsice,
i.e. vrshr_* and vrshrq_* [1]. It also moves the corresponding tests
from:
* clang/test/CodeGen/AArch64/neon_intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/intrinsics.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Reference:
[1]https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right
co-authored-by: Md Mouzam Arfi Hussain <arfihussain27 at gmail.com>
>From b05634c7e7f86d1d814c9142dbf17959a06b47fb Mon Sep 17 00:00:00 2001
From: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: Thu, 16 Apr 2026 19:37:44 +0000
Subject: [PATCH] [clang][CIR] Add lowering for vrshr_ and vrshrq_ rounding
intrinsics
This PR adds lowering for the vector rounding shift right intrinsice,
i.e. vrshr_* and vrshrq_* [1]. It also moves the corresponding tests
from:
* clang/test/CodeGen/AArch64/neon_intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/intrinsics.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Reference:
[1]https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right
co-authored-by: Md Mouzam Arfi Hussain <arfihussain27 at gmail.com>
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 34 ++-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 205 ------------------
clang/test/CodeGen/AArch64/neon/intrinsics.c | 205 ++++++++++++++++++
3 files changed, 235 insertions(+), 209 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 294e87168b0e5..6d18a1d3a3c45 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -514,7 +514,7 @@ static mlir::Value emitCommonNeonBuiltinExpr(
cir::VectorType vTy = getNeonType(&cgf, neonType, loc, hasLegalHalfType,
false, allowBFloatArgsAndRet);
- mlir::Type ty = vTy;
+ cir::VectorType ty = vTy;
if (!ty)
return nullptr;
@@ -746,8 +746,21 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vrsqrteq_v:
case NEON::BI__builtin_neon_vrndi_v:
case NEON::BI__builtin_neon_vrndiq_v:
+ cgf.cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ ctx.BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vrshr_n_v:
- case NEON::BI__builtin_neon_vrshrq_n_v:
+ case NEON::BI__builtin_neon_vrshrq_n_v: {
+ llvm::StringRef intrName =
+ usgn ? "aarch64.neon.urshl" : "aarch64.neon.srshl";
+ return emitNeonCall(
+ cgf.cgm, cgf.getBuilder(),
+ {ty, usgn ? getSignChangedVectorType(cgf.getBuilder(), ty) : ty}, ops,
+ intrName, ty, loc, /*isConstrainedFPIntrinsic=*/false,
+ /*shift=*/1,
+ /*rightshift=*/true);
+ }
case NEON::BI__builtin_neon_vsha512hq_u64:
case NEON::BI__builtin_neon_vsha512h2q_u64:
case NEON::BI__builtin_neon_vsha512su0q_u64:
@@ -2352,12 +2365,25 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vqshlud_n_s64:
case NEON::BI__builtin_neon_vqshld_n_u64:
case NEON::BI__builtin_neon_vqshld_n_s64:
- case NEON::BI__builtin_neon_vrshrd_n_u64:
- case NEON::BI__builtin_neon_vrshrd_n_s64:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
+ case NEON::BI__builtin_neon_vrshrd_n_u64:
+ case NEON::BI__builtin_neon_vrshrd_n_s64: {
+ llvm::StringRef intrName = builtinID == NEON::BI__builtin_neon_vrshrd_n_s64
+ ? "aarch64.neon.srshl"
+ : "aarch64.neon.urshl";
+ cir::IntType int64Ty = builtinID == NEON::BI__builtin_neon_vqshld_n_u64
+ ? builder.getUInt64Ty()
+ : builder.getSInt64Ty();
+ int64_t sv = -cast<cir::IntAttr>(
+ cast<cir::ConstantOp>(ops[1].getDefiningOp()).getValue())
+ .getSInt();
+ ops[1] = builder.getSInt64(sv, loc);
+ return emitNeonCall(cgm, builder, {int64Ty, builder.getSInt64Ty()}, ops,
+ intrName, int64Ty, loc);
+ }
case NEON::BI__builtin_neon_vrsrad_n_u64:
case NEON::BI__builtin_neon_vrsrad_n_s64: {
cir::IntType int64Type = builtinID == NEON::BI__builtin_neon_vrsrad_n_u64
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 920a0236bb433..32f382001ba7c 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -5605,167 +5605,6 @@ uint64x2_t test_vsraq_n_u64(uint64x2_t a, uint64x2_t b) {
return vsraq_n_u64(a, b, 3);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vrshr_n_s8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]
-//
-int8x8_t test_vrshr_n_s8(int8x8_t a) {
- return vrshr_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vrshr_n_s16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]
-//
-int16x4_t test_vrshr_n_s16(int16x4_t a) {
- return vrshr_n_s16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vrshr_n_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <2 x i32> [[VRSHR_N1]]
-//
-int32x2_t test_vrshr_n_s32(int32x2_t a) {
- return vrshr_n_s32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vrshrq_n_s8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
-//
-int8x16_t test_vrshrq_n_s8(int8x16_t a) {
- return vrshrq_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vrshrq_n_s16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
-//
-int16x8_t test_vrshrq_n_s16(int16x8_t a) {
- return vrshrq_n_s16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vrshrq_n_s32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
-//
-int32x4_t test_vrshrq_n_s32(int32x4_t a) {
- return vrshrq_n_s32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vrshrq_n_s64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
-// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
-//
-int64x2_t test_vrshrq_n_s64(int64x2_t a) {
- return vrshrq_n_s64(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vrshr_n_u8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]
-//
-uint8x8_t test_vrshr_n_u8(uint8x8_t a) {
- return vrshr_n_u8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vrshr_n_u16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]
-//
-uint16x4_t test_vrshr_n_u16(uint16x4_t a) {
- return vrshr_n_u16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vrshr_n_u32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <2 x i32> [[VRSHR_N1]]
-//
-uint32x2_t test_vrshr_n_u32(uint32x2_t a) {
- return vrshr_n_u32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vrshrq_n_u8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
-// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
-//
-uint8x16_t test_vrshrq_n_u8(uint8x16_t a) {
- return vrshrq_n_u8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vrshrq_n_u16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
-// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
-//
-uint16x8_t test_vrshrq_n_u16(uint16x8_t a) {
- return vrshrq_n_u16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vrshrq_n_u32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3))
-// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
-//
-uint32x4_t test_vrshrq_n_u32(uint32x4_t a) {
- return vrshrq_n_u32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vrshrq_n_u64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
-// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
-//
-uint64x2_t test_vrshrq_n_u64(uint64x2_t a) {
- return vrshrq_n_u64(a, 3);
-}
-
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vsri_n_s8(
// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -15569,50 +15408,6 @@ uint64_t test_vcaltd_f64(float64_t a, float64_t b) {
return (uint64_t)vcaltd_f64(a, b);
}
-// CHECK-LABEL: define dso_local i64 @test_vrshrd_n_s64(
-// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[A]], i64 -63)
-// CHECK-NEXT: ret i64 [[VRSHR_N]]
-//
-int64_t test_vrshrd_n_s64(int64_t a) {
- return (int64_t)vrshrd_n_s64(a, 63);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vrshr_n_s64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1))
-// CHECK-NEXT: ret <1 x i64> [[VRSHR_N1]]
-//
-int64x1_t test_vrshr_n_s64(int64x1_t a) {
- return vrshr_n_s64(a, 1);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vrshrd_n_u64(
-// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VRSHR_N:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[A]], i64 -63)
-// CHECK-NEXT: ret i64 [[VRSHR_N]]
-//
-uint64_t test_vrshrd_n_u64(uint64_t a) {
- return (uint64_t)vrshrd_n_u64(a, 63);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vrshr_n_u64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1))
-// CHECK-NEXT: ret <1 x i64> [[VRSHR_N1]]
-//
-uint64x1_t test_vrshr_n_u64(uint64x1_t a) {
- return vrshr_n_u64(a, 1);
-}
-
// CHECK-LABEL: define dso_local i64 @test_vsrad_n_s64(
// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index bf14d1abc9d8e..7234434d35f33 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -4253,3 +4253,208 @@ float64_t test_vminnmvq_f64(float64x2_t a) {
// LLVM-NEXT: ret double [[VMINNMVQ_F64_I]]
return vminnmvq_f64(a);
}
+
+//===----------------------------------------------------------------------===//
+// 2.1.3.2.2 Vector rounding shift right
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right
+//===----------------------------------------------------------------------===//
+// ALL-LABEL: @test_vrshr_n_s8(
+int8x8_t test_vrshr_n_s8(int8x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
+// LLVM: ret <8 x i8> [[VRSHR_N]]
+ return vrshr_n_s8(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_s16(
+int16x4_t test_vrshr_n_s16(int16x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+// LLVM: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+// LLVM: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
+// LLVM: ret <4 x i16> [[VRSHR_N1]]
+ return vrshr_n_s16(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_s32(
+int32x2_t test_vrshr_n_s32(int32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// CHECK: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// CHECK: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
+// CHECK: ret <2 x i32> [[VRSHR_N1]]
+ return vrshr_n_s32(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_s64(
+int64x1_t test_vrshr_n_s64(int64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// CHECK: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
+// CHECK: ret <16 x i8> [[VRSHR_N]]
+ return vrshr_n_s64(a, 1);
+}
+
+// ALL-LABEL: @test_vrshr_n_u8(
+uint8x8_t test_vrshr_n_u8(uint8x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -3))
+// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]
+ return vrshr_n_u8(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_u16(
+uint16x4_t test_vrshr_n_u16(uint16x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <4 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3))
+// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]
+ return vrshr_n_u16(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_u32(
+uint32x2_t test_vrshr_n_u32(uint32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <2 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3))
+// CHECK-NEXT: ret <2 x i32> [[VRSHR_N1]]
+ return vrshr_n_u32(a, 3);
+}
+
+// ALL-LABEL: @test_vrshr_n_u64(
+uint64x1_t test_vrshr_n_u64(uint64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <1 x i64> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1))
+// CHECK-NEXT: ret <1 x i64> [[VRSHR_N1]]
+ return vrshr_n_u64(a, 1);
+}
+
+// ALL-LABEL: @test_vrshrq_n_s8(
+int8x16_t test_vrshrq_n_s8(int8x16_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
+// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
+ return vrshrq_n_s8(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_s16(
+int16x8_t test_vrshrq_n_s16(int16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <8 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
+// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
+ return vrshrq_n_s16(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_s32(
+int32x4_t test_vrshrq_n_s32(int32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3))
+// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
+ return vrshrq_n_s32(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_s64(
+int64x2_t test_vrshrq_n_s64(int64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
+// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
+ return vrshrq_n_s64(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_u8(
+uint8x16_t test_vrshrq_n_u8(uint8x16_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 -3))
+// CHECK-NEXT: ret <16 x i8> [[VRSHR_N]]
+ return vrshrq_n_u8(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_u16(
+uint16x8_t test_vrshrq_n_u16(uint16x8_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3))
+// CHECK-NEXT: ret <8 x i16> [[VRSHR_N1]]
+ return vrshrq_n_u16(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_u32(
+uint32x4_t test_vrshrq_n_u32(uint32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// CHECK-NEXT: ret <4 x i32> [[VRSHR_N1]]
+ return vrshrq_n_u32(a, 3);
+}
+
+// ALL-LABEL: @test_vrshrq_n_u64(
+uint64x2_t test_vrshrq_n_u64(uint64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3))
+// CHECK-NEXT: ret <2 x i64> [[VRSHR_N1]]
+ return vrshrq_n_u64(a, 3);
+}
+
+// vrshrd_n_* (scalar 64-bit)
+// ALL-LABEL: @test_vrshrd_n_s64(
+int64_t test_vrshrd_n_s64(int64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.srshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: i64 {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[VRSHR_N:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[A]], i64 -63)
+// CHECK-NEXT: ret i64 [[VRSHR_N]]
+ return (int64_t)vrshrd_n_s64(a, 63);
+}
+
+// ALL-LABEL: @test_vrshrd_n_u64(
+uint64_t test_vrshrd_n_u64(uint64_t a) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.urshl" {{%.*}}, {{%.*}}
+
+// CHECK-SAME: i64 {{.*}} [[A:%.*]])
+// CHECK-NEXT: [[VRSHR_N:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[A]], i64 -63)
+ return (uint64_t)vrshrd_n_u64(a, 63);
+}
More information about the cfe-commits
mailing list