[clang] a48159d - [AArch64][llvm] Remove support for FEAT_MPAMv2_VID (#193191)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Apr 24 04:01:37 PDT 2026
Author: Jonathan Thackray
Date: 2026-04-24T12:01:32+01:00
New Revision: a48159df9ce57c2bf377588b52563966865514a2
URL: https://github.com/llvm/llvm-project/commit/a48159df9ce57c2bf377588b52563966865514a2
DIFF: https://github.com/llvm/llvm-project/commit/a48159df9ce57c2bf377588b52563966865514a2.diff
LOG: [AArch64][llvm] Remove support for FEAT_MPAMv2_VID (#193191)
`FEAT_MPAMv2_VID` instructions and system registers, as introduced
in change d30f18d2c, are being removed at this time, as they've been
removed from the latest Arm ARM, which doesn't preclude them returning
in some form in future.
Other system registers introduced with `FEAT_MPAMv2` are unaffected,
and these continue to be ungated, but since `+mpamv2` gating is now
empty,
I'm removing this superfluous gating code.
Added:
Modified:
clang/test/Driver/aarch64-v97a.c
clang/test/Driver/print-supported-extensions-aarch64.c
llvm/lib/Target/AArch64/AArch64Features.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll
llvm/test/MC/AArch64/armv9.7a-mpamv2.s
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
################################################################################
diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c
index 04252a0ddc603..51046aa935a2c 100644
--- a/clang/test/Driver/aarch64-v97a.c
+++ b/clang/test/Driver/aarch64-v97a.c
@@ -42,10 +42,6 @@
// RUN: %clang -target aarch64 -march=armv9.7-a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
// V97A-TLBID: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tlbid"
-// RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
-// RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
-// V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"
-
// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s
// V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 33e26d3c25e02..89db42f70f201 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -50,7 +50,6 @@
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
// CHECK-NEXT: mops-go FEAT_MOPS_GO Enable memset acceleration granule only
-// CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
// CHECK-NEXT: mtetc FEAT_MTETC Enable Virtual Memory Tagging Extension
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 0c3d757da8f6b..8cd2278a05747 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -590,9 +590,6 @@ def FeatureLSCP : ExtensionWithMArch<"lscp", "LSCP", "FEAT_LSCP",
def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
"Enable Armv9.7-A TLBI Domains extension">;
-def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
- "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;
-
def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC",
"Enable Virtual Memory Tagging Extension", [FeatureMTE]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index ca377de8deb78..f30dd16ec76db 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -395,8 +395,6 @@ def HasCPA : Predicate<"Subtarget->hasCPA()">,
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
-def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,
- AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
def HasMTETC : Predicate<"Subtarget->hasMTETC()">,
AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;
def HasGCIE : Predicate<"Subtarget->hasGCIE()">,
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index fb1f58d854135..bcd1786a0e9ea 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2413,9 +2413,6 @@ def : RWSysReg<"MPAMCTL_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b010>;
-def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;
-def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;
-def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;
// v9.7a General Improvements
// Op0 Op1 CRn CRm Op2
@@ -2526,39 +2523,6 @@ foreach n = 0-3 in {
def : ROSysReg<"TLBIDIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b110>;
-// MPAM Lookaside Buffer Invalidate (MLBI) instructions
-class MLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
- string Name = name;
- bits<14> Encoding;
- let Encoding{13-11} = op1;
- let Encoding{10-7} = crn;
- let Encoding{6-3} = crm;
- let Encoding{2-0} = op2;
- bit NeedsReg = needsreg;
- string RequiresStr = [{ {AArch64::FeatureMPAMv2} }];
-}
-
-def MLBITable : GenericTable {
- let FilterClass = "MLBI";
- let CppTypeName = "MLBI";
- let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
-
- let PrimaryKey = ["Encoding"];
- let PrimaryKeyName = "lookupMLBIByEncoding";
-}
-
-def lookupMLBIByName : SearchIndex {
- let Table = MLBITable;
- let Key = ["Name"];
-}
-
-// Op1 CRn CRm Op2 needsReg
-def : MLBI<"ALLE1", 0b100, 0b0111, 0b0000, 0b100, 0>;
-def : MLBI<"VMALLE1", 0b100, 0b0111, 0b0000, 0b101, 0>;
-def : MLBI<"VPIDE1", 0b100, 0b0111, 0b0000, 0b110, 1>;
-def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>;
-
-
// v9.7-A GICv5 (FEAT_GCIE)
// CPU Interface Registers
// Op0 Op1 CRn CRm Op2
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 906117a066dd6..28417db66709b 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3940,7 +3940,6 @@ static const struct Extension {
{"sme-tmop", {AArch64::FeatureSME_TMOP}},
{"lscp", {AArch64::FeatureLSCP}},
{"tlbid", {AArch64::FeatureTLBID}},
- {"mpamv2", {AArch64::FeatureMPAMv2}},
{"mtetc", {AArch64::FeatureMTETC}},
{"gcie", {AArch64::FeatureGCIE}},
{"sme2p3", {AArch64::FeatureSME2p3}},
@@ -4033,9 +4032,9 @@ void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands
AArch64Operand::CreateImm(Expr, S, getLoc(), getContext()));
}
-/// parseSysAlias - The IC, DC, AT, TLBI, MLBI and GIC{R} and GSB instructions
-/// are simple aliases for the SYS instruction. Parse them specially so that
-/// we create a SYS MCInst.
+/// parseSysAlias - The IC, DC, AT, TLBI and GIC{R} and GSB instructions are
+/// simple aliases for the SYS instruction. Parse them specially so that we
+/// create a SYS MCInst.
bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
if (Name.contains('.'))
@@ -4096,17 +4095,6 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
if (hasAll || hasTLBID)
OptionalRegister = TLBI->RegUse == REG_OPTIONAL;
createSysAlias(TLBI->Encoding, Operands, S);
- } else if (Mnemonic == "mlbi") {
- const AArch64MLBI::MLBI *MLBI = AArch64MLBI::lookupMLBIByName(Op);
- if (!MLBI)
- return TokError("invalid operand for MLBI instruction");
- else if (!MLBI->haveFeatures(getSTI().getFeatureBits())) {
- std::string Str("MLBI " + std::string(MLBI->Name) + " requires: ");
- setRequiredFeatureString(MLBI->getRequiredFeatures(), Str);
- return TokError(Str);
- }
- ExpectRegister = MLBI->NeedsReg;
- createSysAlias(MLBI->Encoding, Operands, S);
} else if (Mnemonic == "gic") {
const AArch64GIC::GIC *GIC = AArch64GIC::lookupGICByName(Op);
if (!GIC)
@@ -5506,11 +5494,11 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next);
- // IC, DC, AT, TLBI, MLBI, PLBI, GIC{R}, GSB and Prediction invalidation
+ // IC, DC, AT, TLBI, PLBI, GIC{R}, GSB and Prediction invalidation
// instructions are aliases for the SYS instruction.
if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi" ||
Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp" ||
- Head == "mlbi" || Head == "plbi" || Head == "gic" || Head == "gsb")
+ Head == "plbi" || Head == "gic" || Head == "gsb")
return parseSysAlias(Head, NameLoc, Operands);
// GICR instructions are aliases for the SYSL instruction.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 2f4b3fa016336..2df769539960d 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -922,18 +922,8 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
if (CnVal == 7) {
switch (CmVal) {
- default: return false;
- // MLBI aliases
- case 0: {
- const AArch64MLBI::MLBI *MLBI =
- AArch64MLBI::lookupMLBIByEncoding(Encoding);
- if (!MLBI || !MLBI->haveFeatures(STI.getFeatureBits()))
- return false;
-
- NeedsReg = MLBI->NeedsReg;
- Ins = "mlbi\t";
- Name = std::string(MLBI->Name);
- } break;
+ default:
+ return false;
// Maybe IC, maybe Prediction Restriction
case 1:
switch (Op1Val) {
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
index 556d2c32569b4..c2fccc91cfec9 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -211,11 +211,6 @@ namespace AArch64TLBIP {
#define GET_TLBIPTable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP
-
-namespace AArch64MLBI {
-#define GET_MLBITable_IMPL
-#include "AArch64GenSystemOperands.inc"
-} // namespace AArch64MLBI
} // namespace llvm
namespace llvm {
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 3411b28d616d9..1f18af709bd93 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -880,14 +880,6 @@ struct TLBIP : TLBIPSysAlias {
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP
-namespace AArch64MLBI {
-struct MLBI : SysAliasReg {
- using SysAliasReg::SysAliasReg;
-};
-#define GET_MLBITable_DECL
-#include "AArch64GenSystemOperands.inc"
-} // namespace AArch64MLBI
-
namespace AArch64GIC {
struct GIC : SysAliasReg {
using SysAliasReg::SysAliasReg;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll b/llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll
index 79ee54a97e53a..8fe497dcb2f56 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll
@@ -3,7 +3,6 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+specres2 -asm-verbose=false | FileCheck %s --check-prefix=SPECRES2
; RUN: llc < %s -mtriple=aarch64 -mattr=+gcie -asm-verbose=false | FileCheck %s --check-prefix=GCIE
; RUN: llc < %s -mtriple=aarch64 -mattr=+poe2 -asm-verbose=false | FileCheck %s --check-prefix=POE2
-; RUN: llc < %s -mtriple=aarch64 -mattr=+mpamv2 -asm-verbose=false | FileCheck %s --check-prefix=MPAMV2
declare void @llvm.aarch64.sys(i32 immarg, i32 immarg, i32 immarg, i32 immarg,
i64)
@@ -115,12 +114,3 @@ entry:
call void @llvm.aarch64.sys(i32 0, i32 10, i32 7, i32 0, i64 0)
ret void
}
-
-define void @sys_mlbi_vmalle1() {
-; MPAMV2-LABEL: sys_mlbi_vmalle1:
-; MPAMV2: mlbi vmalle1
-; MPAMV2-NEXT: ret
-entry:
- call void @llvm.aarch64.sys(i32 4, i32 7, i32 0, i32 5, i64 0)
- ret void
-}
diff --git a/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
deleted file mode 100644
index 54fdc230a3a10..0000000000000
--- a/llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
+++ /dev/null
@@ -1,18 +0,0 @@
-// RUN: not llvm-mc -triple=aarch64 -mattr=+mpamv2 -show-encoding < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-
-//------------------------------------------------------------------------------
-// Armv9.7-A FEAT_MPAMV2 Extensions
-//------------------------------------------------------------------------------
-
-mlbi alle1, x30
-// CHECK-ERROR: error: specified mlbi op does not use a register
-
-mlbi vmalle1, x30
-// CHECK-ERROR: error: specified mlbi op does not use a register
-
-mlbi vpide1
-// CHECK-ERROR: error: specified mlbi op requires a register
-
-mlbi vpmge1
-// CHECK-ERROR: error: specified mlbi op requires a register
diff --git a/llvm/test/MC/AArch64/armv9.7a-mpamv2.s b/llvm/test/MC/AArch64/armv9.7a-mpamv2.s
index b8b21e96869f3..c114b3f4d15c1 100644
--- a/llvm/test/MC/AArch64/armv9.7a-mpamv2.s
+++ b/llvm/test/MC/AArch64/armv9.7a-mpamv2.s
@@ -1,15 +1,11 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \
-// RUN: | llvm-objdump -d --mattr=+mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \
-// RUN: | llvm-objdump -d --mattr=-mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+mpamv2 -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
//------------------------------------------------------------------------------
@@ -19,108 +15,31 @@
msr MPAMCTL_EL1, x0
// CHECK-INST: msr MPAMCTL_EL1, x0
// CHECK-ENCODING: [0x40,0xa5,0x18,0xd5]
-// CHECK-UNKNOWN: d518a540
msr MPAMCTL_EL12, x0
// CHECK-INST: msr MPAMCTL_EL12, x0
// CHECK-ENCODING: [0x40,0xa5,0x1d,0xd5]
-// CHECK-UNKNOWN: d51da540
msr MPAMCTL_EL2, x0
// CHECK-INST: msr MPAMCTL_EL2, x0
// CHECK-ENCODING: [0x40,0xa5,0x1c,0xd5]
-// CHECK-UNKNOWN: d51ca540
msr MPAMCTL_EL3, x0
// CHECK-INST: msr MPAMCTL_EL3, x0
// CHECK-ENCODING: [0x40,0xa5,0x1e,0xd5]
-// CHECK-UNKNOWN: d51ea540
-
-msr MPAMVIDCR_EL2, x0
-// CHECK-INST: msr MPAMVIDCR_EL2, x0
-// CHECK-ENCODING: [0x00,0xa7,0x1c,0xd5]
-// CHECK-UNKNOWN: d51ca700
-
-msr MPAMVIDSR_EL2, x0
-// CHECK-INST: msr MPAMVIDSR_EL2, x0
-// CHECK-ENCODING: [0x20,0xa7,0x1c,0xd5]
-// CHECK-UNKNOWN: d51ca720
-
-msr MPAMVIDSR_EL3, x0
-// CHECK-INST: msr MPAMVIDSR_EL3, x0
-// CHECK-ENCODING: [0x20,0xa7,0x1e,0xd5]
-// CHECK-UNKNOWN: d51ea720
-
mrs x0, MPAMCTL_EL1
// CHECK-INST: mrs x0, MPAMCTL_EL1
// CHECK-ENCODING: [0x40,0xa5,0x38,0xd5]
-// CHECK-UNKNOWN: d538a540
mrs x0, MPAMCTL_EL12
// CHECK-INST: mrs x0, MPAMCTL_EL12
// CHECK-ENCODING: [0x40,0xa5,0x3d,0xd5]
-// CHECK-UNKNOWN: d53da540
mrs x0, MPAMCTL_EL2
// CHECK-INST: mrs x0, MPAMCTL_EL2
// CHECK-ENCODING: [0x40,0xa5,0x3c,0xd5]
-// CHECK-UNKNOWN: d53ca540
mrs x0, MPAMCTL_EL3
// CHECK-INST: mrs x0, MPAMCTL_EL3
// CHECK-ENCODING: [0x40,0xa5,0x3e,0xd5]
-// CHECK-UNKNOWN: d53ea540
-
-mrs x0, MPAMVIDCR_EL2
-// CHECK-INST: mrs x0, MPAMVIDCR_EL2
-// CHECK-ENCODING: [0x00,0xa7,0x3c,0xd5]
-// CHECK-UNKNOWN: d53ca700
-
-mrs x0, MPAMVIDSR_EL2
-// CHECK-INST: mrs x0, MPAMVIDSR_EL2
-// CHECK-ENCODING: [0x20,0xa7,0x3c,0xd5]
-// CHECK-UNKNOWN: d53ca720
-
-mrs x0, MPAMVIDSR_EL3
-// CHECK-INST: mrs x0, MPAMVIDSR_EL3
-// CHECK-ENCODING: [0x20,0xa7,0x3e,0xd5]
-// CHECK-UNKNOWN: d53ea720
-
-
-//------------------------------------------------------------------------------
-// Armv9.7-A FEAT_MPAMV2_VID Extensions
-//------------------------------------------------------------------------------
-
-mlbi vmalle1
-// CHECK-INST: mlbi vmalle1
-// CHECK-ENCODING: [0xbf,0x70,0x0c,0xd5]
-// CHECK-UNKNOWN: d50c70bf sys #4, c7, c0, #5
-// CHECK-ERROR: error: MLBI VMALLE1 requires: mpamv2
-
-mlbi vpide1, x0
-// CHECK-INST: mlbi vpide1, x0
-// CHECK-ENCODING: [0xc0,0x70,0x0c,0xd5]
-// CHECK-UNKNOWN: d50c70c0 sys #4, c7, c0, #6, x0
-// CHECK-ERROR: error: MLBI VPIDE1 requires: mpamv2
-
-mlbi vpmge1, x0
-// CHECK-INST: mlbi vpmge1, x0
-// CHECK-ENCODING: [0xe0,0x70,0x0c,0xd5]
-// CHECK-UNKNOWN: d50c70e0 sys #4, c7, c0, #7, x0
-// CHECK-ERROR: error: MLBI VPMGE1 requires: mpamv2
-
-// Check that invalid encodings are rendered as SYS aliases
-// [0x9f,0x70,0x0c,0xd5] -> mlbi alle1
-// [0x9e,0x70,0x0c,0xd5] -> sys #4, c7, c0, #4, x30
-
-mlbi alle1
-// CHECK-INST: mlbi alle1
-// CHECK-ENCODING: [0x9f,0x70,0x0c,0xd5]
-// CHECK-UNKNOWN: d50c709f sys #4, c7, c0, #4
-// CHECK-ERROR: error: MLBI ALLE1 requires: mpamv2
-
-sys #4, c7, c0, #4, x30
-// CHECK-INST: sys #4, c7, c0, #4, x30
-// CHECK-ENCODING: [0x9e,0x70,0x0c,0xd5]
-// CHECK-UNKNOWN: d50c709e sys #4, c7, c0, #4, x30
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 835c9415dffa1..6377b197d911e 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1452,7 +1452,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SME_TMOP, AArch64::AEK_SVEBITPERM,
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
AArch64::AEK_LSCP, AArch64::AEK_TLBID,
- AArch64::AEK_MPAMV2, AArch64::AEK_MTETC,
AArch64::AEK_GCIE, AArch64::AEK_SME2P3,
AArch64::AEK_SVE2P3, AArch64::AEK_SVE_B16MM,
AArch64::AEK_F16MM, AArch64::AEK_F16F32DOT,
@@ -1460,6 +1459,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_POE2, AArch64::AEK_TEV,
AArch64::AEK_BTIE, AArch64::AEK_F64MM,
AArch64::AEK_POPS, AArch64::AEK_SVESM4,
+ AArch64::AEK_MTETC,
};
std::vector<StringRef> Features;
@@ -1571,7 +1571,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sme-tmop"));
EXPECT_TRUE(llvm::is_contained(Features, "+lscp"));
EXPECT_TRUE(llvm::is_contained(Features, "+tlbid"));
- EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2"));
EXPECT_TRUE(llvm::is_contained(Features, "+mtetc"));
EXPECT_TRUE(llvm::is_contained(Features, "+gcie"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme2p3"));
@@ -1750,7 +1749,6 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sme-tmop", "nosme-tmop", "+sme-tmop", "-sme-tmop"},
{"lscp", "nolscp", "+lscp", "-lscp"},
{"tlbid", "notlbid", "+tlbid", "-tlbid"},
- {"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"},
{"mtetc", "nomtetc", "+mtetc", "-mtetc"},
{"gcie", "nogcie", "+gcie", "-gcie"},
{"sme2p3", "nosme2p3", "+sme2p3", "-sme2p3"},
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