[clang] [CIR][AArch64] Lower NEON vzip intrinsics (PR #193658)
Jiahao Guo via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 22 21:14:56 PDT 2026
https://github.com/E00N777 created https://github.com/llvm/llvm-project/pull/193658
### Summary
Lower NEON::BI__builtin_neon_vzip_v and NEON::BI__builtin_neon_vzipq_v in CIRGenBuiltinAArch64.cpp by porting the existing incubator logic (`clangir/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp`) onto ClangIR: two bitcasts on the input vectors, two rounds of cir.vec.shuffle generating the low/high interleave patterns, each stored through a ptr_stride of the sret base pointer.
### Test
- test_vzip_mf8
- test_vzipq_mf8
I found that these two intrinsics are defined in `llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c`, but this file seems to be a test suite specifically for the `mfloat8` type, so I did not remove their original test cases.
Some of the new CHECK lines additionally match a pair of bitcasts before the shuffle; this shape comes from arm_neon.h's inline wrappers, which re-cast typed vectors (e.g. <4 x i16>) through <8 x i8> before calling __builtin_neon_vzip_v. Variants whose element type is already i8 (s8/u8/p8/mf8) skip that round-trip and therefore have no bitcasts in the check lines.
>From aba1d3425ed2617a27d487ab3e536d30db0fed5f Mon Sep 17 00:00:00 2001
From: E0N777 <E0N_gjh at 163.com>
Date: Thu, 23 Apr 2026 11:42:52 +0800
Subject: [PATCH] [CIR][AArch64] Lower NEON vzip intrinsics
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 25 +-
clang/test/CodeGen/AArch64/neon/intrinsics.c | 357 +++++++++++++++++
clang/test/CodeGen/arm_neon_intrinsics.c | 376 ------------------
3 files changed, 381 insertions(+), 377 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index ace8a5737f4bd..a8ee0aae07da9 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2774,8 +2774,31 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vtrnq_v:
case NEON::BI__builtin_neon_vuzp_v:
case NEON::BI__builtin_neon_vuzpq_v:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vzip_v:
- case NEON::BI__builtin_neon_vzipq_v:
+ case NEON::BI__builtin_neon_vzipq_v: {
+ ops[1] = builder.createBitcast(ops[1], ty);
+ ops[2] = builder.createBitcast(ops[2], ty);
+ // Adding a bitcast here as Ops[0] might be a void pointer.
+ mlir::Value baseAddr =
+ builder.createBitcast(ops[0], builder.getPointerTo(ty));
+ mlir::Value sv;
+ for (unsigned vi = 0; vi != 2; ++vi) {
+ llvm::SmallVector<int64_t, 16> indices;
+ for (unsigned i = 0, e = ty.getSize(); i != e; i += 2) {
+ indices.push_back((i + vi * e) >> 1);
+ indices.push_back(((i + vi * e) >> 1) + e);
+ }
+ cir::ConstantOp idx = builder.getConstInt(loc, builder.getSInt32Ty(), vi);
+ mlir::Value addr = builder.createPtrStride(loc, baseAddr, idx);
+ sv = builder.createVecShuffle(loc, ops[1], ops[2], indices);
+ (void)builder.CIRBaseBuilderTy::createStore(loc, sv, addr);
+ }
+ return sv;
+ }
case NEON::BI__builtin_neon_vqtbl1q_v:
case NEON::BI__builtin_neon_vqtbl2q_v:
case NEON::BI__builtin_neon_vqtbl3q_v:
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b8863168d2886..d2574a4f5ccbf 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -4165,3 +4165,360 @@ float64_t test_vminnmvq_f64(float64x2_t a) {
// LLVM-NEXT: ret double [[VMINNMVQ_F64_I]]
return vminnmvq_f64(a);
}
+
+//===------------------------------------------------------===//
+// 2.1.9.10. Zip elements
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#zip-elements
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vzip_s8(
+// CIR-LABEL: @vzip_s8(
+int8x8x2_t test_vzip_s8(int8x8_t a, int8x8_t b) {
+ // CIR: [[LO:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !s8i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !s8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !s8i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !s8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+
+ // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzip_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_s16(
+// CIR-LABEL: @vzip_s16(
+int16x4x2_t test_vzip_s16(int16x4_t a, int16x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !s16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !s16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s16i>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !s16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s16i>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !s16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+
+ // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <8 x i8> [[A_RAW]] to <4 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <8 x i8> [[B_RAW]] to <4 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzip_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_u8(
+// CIR-LABEL: @vzip_u8(
+uint8x8x2_t test_vzip_u8(uint8x8_t a, uint8x8_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<8 x !u8i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<8 x !u8i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u8i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !u8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u8i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !u8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+
+ // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzip_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_u16(
+// CIR-LABEL: @vzip_u16(
+uint16x4x2_t test_vzip_u16(uint16x4_t a, uint16x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !u16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !u16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !u16i>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !u16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !u16i>, !cir.ptr<!cir.vector<4 x !u16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !u16i>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !u16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !u16i>, !cir.ptr<!cir.vector<4 x !u16i>>
+
+ // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <8 x i8> [[A_RAW]] to <4 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <8 x i8> [[B_RAW]] to <4 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzip_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_p8(
+// CIR-LABEL: @vzip_p8(
+poly8x8x2_t test_vzip_p8(poly8x8_t a, poly8x8_t b) {
+ // CIR: [[LO:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !s8i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !s8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !s8i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !s8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+
+ // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzip_p8(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_p16(
+// CIR-LABEL: @vzip_p16(
+poly16x4x2_t test_vzip_p16(poly16x4_t a, poly16x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !s16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<4 x !s16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s16i>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !s16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s16i>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !s16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+
+ // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <8 x i8> [[A_RAW]] to <4 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <8 x i8> [[B_RAW]] to <4 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x i16> [[A_CAST]], <4 x i16> [[B_CAST]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzip_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_mf8(
+// CIR-LABEL: @vzip_mf8(
+mfloat8x8x2_t test_vzip_mf8(mfloat8x8_t a, mfloat8x8_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<8 x !u8i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<8 x !u8i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u8i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !u8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u8i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !u8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+
+ // LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzip_mf8(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_s32(
+// CIR-LABEL: @vzip_s32(
+int32x2x2_t test_vzip_s32(int32x2_t a, int32x2_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !s32i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !s32i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !s32i>) [#cir.int<0> : !s32i, #cir.int<2> : !s32i] : !cir.vector<2 x !s32i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<2 x !s32i>, !cir.ptr<!cir.vector<2 x !s32i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !s32i>) [#cir.int<1> : !s32i, #cir.int<3> : !s32i] : !cir.vector<2 x !s32i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<2 x !s32i>, !cir.ptr<!cir.vector<2 x !s32i>>
+
+ // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <8 x i8> [[A_RAW]] to <2 x i32>
+ // LLVM: [[B_CAST:%.*]] = bitcast <8 x i8> [[B_RAW]] to <2 x i32>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <2 x i32> [[A_CAST]], <2 x i32> [[B_CAST]], <2 x i32> <i32 0, i32 2>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <2 x i32> [[A_CAST]], <2 x i32> [[B_CAST]], <2 x i32> <i32 1, i32 3>
+ return vzip_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_f32(
+// CIR-LABEL: @vzip_f32(
+float32x2x2_t test_vzip_f32(float32x2_t a, float32x2_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !cir.float>) [#cir.int<0> : !s32i, #cir.int<2> : !s32i] : !cir.vector<2 x !cir.float>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<2 x !cir.float>, !cir.ptr<!cir.vector<2 x !cir.float>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !cir.float>) [#cir.int<1> : !s32i, #cir.int<3> : !s32i] : !cir.vector<2 x !cir.float>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<2 x !cir.float>, !cir.ptr<!cir.vector<2 x !cir.float>>
+
+ // LLVM-SAME: <2 x float> {{.*}} [[A:%.*]], <2 x float> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <2 x float> {{.*}}, <2 x float> {{.*}}, <2 x i32> <i32 0, i32 2>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <2 x float> {{.*}}, <2 x float> {{.*}}, <2 x i32> <i32 1, i32 3>
+ return vzip_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vzip_u32(
+// CIR-LABEL: @vzip_u32(
+uint32x2x2_t test_vzip_u32(uint32x2_t a, uint32x2_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !u32i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s8i> -> !cir.vector<2 x !u32i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !u32i>) [#cir.int<0> : !s32i, #cir.int<2> : !s32i] : !cir.vector<2 x !u32i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<2 x !u32i>, !cir.ptr<!cir.vector<2 x !u32i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<2 x !u32i>) [#cir.int<1> : !s32i, #cir.int<3> : !s32i] : !cir.vector<2 x !u32i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<2 x !u32i>, !cir.ptr<!cir.vector<2 x !u32i>>
+
+ // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <8 x i8> [[A_RAW]] to <2 x i32>
+ // LLVM: [[B_CAST:%.*]] = bitcast <8 x i8> [[B_RAW]] to <2 x i32>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <2 x i32> [[A_CAST]], <2 x i32> [[B_CAST]], <2 x i32> <i32 0, i32 2>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <2 x i32> [[A_CAST]], <2 x i32> [[B_CAST]], <2 x i32> <i32 1, i32 3>
+ return vzip_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_s8(
+// CIR-LABEL: @vzipq_s8(
+int8x16x2_t test_vzipq_s8(int8x16_t a, int8x16_t b) {
+ // CIR: [[LO:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<16 x !s8i>) [#cir.int<0> : !s32i, #cir.int<16> : !s32i, #cir.int<1> : !s32i, #cir.int<17> : !s32i, #cir.int<2> : !s32i, #cir.int<18> : !s32i, #cir.int<3> : !s32i, #cir.int<19> : !s32i, #cir.int<4> : !s32i, #cir.int<20> : !s32i, #cir.int<5> : !s32i, #cir.int<21> : !s32i, #cir.int<6> : !s32i, #cir.int<22> : !s32i, #cir.int<7> : !s32i, #cir.int<23> : !s32i] : !cir.vector<16 x !s8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<16 x !s8i>) [#cir.int<8> : !s32i, #cir.int<24> : !s32i, #cir.int<9> : !s32i, #cir.int<25> : !s32i, #cir.int<10> : !s32i, #cir.int<26> : !s32i, #cir.int<11> : !s32i, #cir.int<27> : !s32i, #cir.int<12> : !s32i, #cir.int<28> : !s32i, #cir.int<13> : !s32i, #cir.int<29> : !s32i, #cir.int<14> : !s32i, #cir.int<30> : !s32i, #cir.int<15> : !s32i, #cir.int<31> : !s32i] : !cir.vector<16 x !s8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+
+ // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ return vzipq_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_s16(
+// CIR-LABEL: @vzipq_s16(
+int16x8x2_t test_vzipq_s16(int16x8_t a, int16x8_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !s16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !s16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !s16i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !s16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !s16i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !s16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+
+ // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <16 x i8> [[A_RAW]] to <8 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <16 x i8> [[B_RAW]] to <8 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzipq_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_s32(
+// CIR-LABEL: @vzipq_s32(
+int32x4x2_t test_vzipq_s32(int32x4_t a, int32x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !s32i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !s32i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !s32i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !s32i>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !s32i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
+
+ // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <16 x i8> [[A_RAW]] to <4 x i32>
+ // LLVM: [[B_CAST:%.*]] = bitcast <16 x i8> [[B_RAW]] to <4 x i32>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x i32> [[A_CAST]], <4 x i32> [[B_CAST]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x i32> [[A_CAST]], <4 x i32> [[B_CAST]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzipq_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_f32(
+// CIR-LABEL: @vzipq_f32(
+float32x4x2_t test_vzipq_f32(float32x4_t a, float32x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !cir.float>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !cir.float>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !cir.float>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !cir.float>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>
+
+ // LLVM-SAME: <4 x float> {{.*}} [[A:%.*]], <4 x float> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzipq_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_u8(
+// CIR-LABEL: @vzipq_u8(
+uint8x16x2_t test_vzipq_u8(uint8x16_t a, uint8x16_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<16 x !u8i>) [#cir.int<0> : !s32i, #cir.int<16> : !s32i, #cir.int<1> : !s32i, #cir.int<17> : !s32i, #cir.int<2> : !s32i, #cir.int<18> : !s32i, #cir.int<3> : !s32i, #cir.int<19> : !s32i, #cir.int<4> : !s32i, #cir.int<20> : !s32i, #cir.int<5> : !s32i, #cir.int<21> : !s32i, #cir.int<6> : !s32i, #cir.int<22> : !s32i, #cir.int<7> : !s32i, #cir.int<23> : !s32i] : !cir.vector<16 x !u8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<16 x !u8i>) [#cir.int<8> : !s32i, #cir.int<24> : !s32i, #cir.int<9> : !s32i, #cir.int<25> : !s32i, #cir.int<10> : !s32i, #cir.int<26> : !s32i, #cir.int<11> : !s32i, #cir.int<27> : !s32i, #cir.int<12> : !s32i, #cir.int<28> : !s32i, #cir.int<13> : !s32i, #cir.int<29> : !s32i, #cir.int<14> : !s32i, #cir.int<30> : !s32i, #cir.int<15> : !s32i, #cir.int<31> : !s32i] : !cir.vector<16 x !u8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+
+ // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ return vzipq_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_u16(
+// CIR-LABEL: @vzipq_u16(
+uint16x8x2_t test_vzipq_u16(uint16x8_t a, uint16x8_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !u16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !u16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u16i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !u16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !u16i>, !cir.ptr<!cir.vector<8 x !u16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !u16i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !u16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !u16i>, !cir.ptr<!cir.vector<8 x !u16i>>
+
+ // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <16 x i8> [[A_RAW]] to <8 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <16 x i8> [[B_RAW]] to <8 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzipq_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_u32(
+// CIR-LABEL: @vzipq_u32(
+uint32x4x2_t test_vzipq_u32(uint32x4_t a, uint32x4_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !u32i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<4 x !u32i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !u32i>) [#cir.int<0> : !s32i, #cir.int<4> : !s32i, #cir.int<1> : !s32i, #cir.int<5> : !s32i] : !cir.vector<4 x !u32i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<4 x !u32i>) [#cir.int<2> : !s32i, #cir.int<6> : !s32i, #cir.int<3> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !u32i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
+
+ // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <16 x i8> [[A_RAW]] to <4 x i32>
+ // LLVM: [[B_CAST:%.*]] = bitcast <16 x i8> [[B_RAW]] to <4 x i32>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <4 x i32> [[A_CAST]], <4 x i32> [[B_CAST]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <4 x i32> [[A_CAST]], <4 x i32> [[B_CAST]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ return vzipq_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_p8(
+// CIR-LABEL: @vzipq_p8(
+poly8x16x2_t test_vzipq_p8(poly8x16_t a, poly8x16_t b) {
+ // CIR: [[LO:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<16 x !s8i>) [#cir.int<0> : !s32i, #cir.int<16> : !s32i, #cir.int<1> : !s32i, #cir.int<17> : !s32i, #cir.int<2> : !s32i, #cir.int<18> : !s32i, #cir.int<3> : !s32i, #cir.int<19> : !s32i, #cir.int<4> : !s32i, #cir.int<20> : !s32i, #cir.int<5> : !s32i, #cir.int<21> : !s32i, #cir.int<6> : !s32i, #cir.int<22> : !s32i, #cir.int<7> : !s32i, #cir.int<23> : !s32i] : !cir.vector<16 x !s8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<16 x !s8i>) [#cir.int<8> : !s32i, #cir.int<24> : !s32i, #cir.int<9> : !s32i, #cir.int<25> : !s32i, #cir.int<10> : !s32i, #cir.int<26> : !s32i, #cir.int<11> : !s32i, #cir.int<27> : !s32i, #cir.int<12> : !s32i, #cir.int<28> : !s32i, #cir.int<13> : !s32i, #cir.int<29> : !s32i, #cir.int<14> : !s32i, #cir.int<30> : !s32i, #cir.int<15> : !s32i, #cir.int<31> : !s32i] : !cir.vector<16 x !s8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+
+ // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ return vzipq_p8(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_p16(
+// CIR-LABEL: @vzipq_p16(
+poly16x8x2_t test_vzipq_p16(poly16x8_t a, poly16x8_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !s16i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<8 x !s16i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !s16i>) [#cir.int<0> : !s32i, #cir.int<8> : !s32i, #cir.int<1> : !s32i, #cir.int<9> : !s32i, #cir.int<2> : !s32i, #cir.int<10> : !s32i, #cir.int<3> : !s32i, #cir.int<11> : !s32i] : !cir.vector<8 x !s16i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<8 x !s16i>) [#cir.int<4> : !s32i, #cir.int<12> : !s32i, #cir.int<5> : !s32i, #cir.int<13> : !s32i, #cir.int<6> : !s32i, #cir.int<14> : !s32i, #cir.int<7> : !s32i, #cir.int<15> : !s32i] : !cir.vector<8 x !s16i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+
+ // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) {{.*}} {
+ // LLVM: [[A_RAW:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[B_RAW:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
+ // LLVM: [[A_CAST:%.*]] = bitcast <16 x i8> [[A_RAW]] to <8 x i16>
+ // LLVM: [[B_CAST:%.*]] = bitcast <16 x i8> [[B_RAW]] to <8 x i16>
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <8 x i16> [[A_CAST]], <8 x i16> [[B_CAST]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ return vzipq_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vzipq_mf8(
+// CIR-LABEL: @vzipq_mf8(
+mfloat8x16x2_t test_vzipq_mf8(mfloat8x16_t a, mfloat8x16_t b) {
+ // CIR: [[A_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
+ // CIR: [[B_CAST:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
+ // CIR: [[LO:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<16 x !u8i>) [#cir.int<0> : !s32i, #cir.int<16> : !s32i, #cir.int<1> : !s32i, #cir.int<17> : !s32i, #cir.int<2> : !s32i, #cir.int<18> : !s32i, #cir.int<3> : !s32i, #cir.int<19> : !s32i, #cir.int<4> : !s32i, #cir.int<20> : !s32i, #cir.int<5> : !s32i, #cir.int<21> : !s32i, #cir.int<6> : !s32i, #cir.int<22> : !s32i, #cir.int<7> : !s32i, #cir.int<23> : !s32i] : !cir.vector<16 x !u8i>
+ // CIR: cir.store [[LO]], %{{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+ // CIR: [[HI:%.*]] = cir.vec.shuffle([[A_CAST]], [[B_CAST]] : !cir.vector<16 x !u8i>) [#cir.int<8> : !s32i, #cir.int<24> : !s32i, #cir.int<9> : !s32i, #cir.int<25> : !s32i, #cir.int<10> : !s32i, #cir.int<26> : !s32i, #cir.int<11> : !s32i, #cir.int<27> : !s32i, #cir.int<12> : !s32i, #cir.int<28> : !s32i, #cir.int<13> : !s32i, #cir.int<29> : !s32i, #cir.int<14> : !s32i, #cir.int<30> : !s32i, #cir.int<15> : !s32i, #cir.int<31> : !s32i] : !cir.vector<16 x !u8i>
+ // CIR: cir.store [[HI]], %{{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+
+ // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) {{.*}} {
+ // LLVM: [[VZIP_LO:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ // LLVM: [[VZIP_HI:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ return vzipq_mf8(a, b);
+}
diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c b/clang/test/CodeGen/arm_neon_intrinsics.c
index eb9fe126ff2a0..c6acc7e2c1483 100644
--- a/clang/test/CodeGen/arm_neon_intrinsics.c
+++ b/clang/test/CodeGen/arm_neon_intrinsics.c
@@ -26822,328 +26822,6 @@ poly8x16x2_t test_vuzpq_p8(poly8x16_t a, poly8x16_t b) {
poly16x8x2_t test_vuzpq_p16(poly16x8_t a, poly16x8_t b) {
return vuzpq_p16(a, b);
}
-
-// CHECK-LABEL: define void @test_vzip_s8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META111]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META111]]
-// CHECK-NEXT: ret void
-//
-int8x8x2_t test_vzip_s8(int8x8_t a, int8x8_t b) {
- return vzip_s8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_s16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META114:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META114]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <4 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META114]]
-// CHECK-NEXT: ret void
-//
-int16x4x2_t test_vzip_s16(int16x4_t a, int16x4_t b) {
- return vzip_s16(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_s32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META117:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 0, i32 2>
-// CHECK-NEXT: store <2 x i32> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META117]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <2 x i32>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 1, i32 3>
-// CHECK-NEXT: store <2 x i32> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META117]]
-// CHECK-NEXT: ret void
-//
-int32x2x2_t test_vzip_s32(int32x2_t a, int32x2_t b) {
- return vzip_s32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_u8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META120]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META120]]
-// CHECK-NEXT: ret void
-//
-uint8x8x2_t test_vzip_u8(uint8x8_t a, uint8x8_t b) {
- return vzip_u8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_u16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META123]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <4 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META123]]
-// CHECK-NEXT: ret void
-//
-uint16x4x2_t test_vzip_u16(uint16x4_t a, uint16x4_t b) {
- return vzip_u16(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_u32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 0, i32 2>
-// CHECK-NEXT: store <2 x i32> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META126]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <2 x i32>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 1, i32 3>
-// CHECK-NEXT: store <2 x i32> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META126]]
-// CHECK-NEXT: ret void
-//
-uint32x2x2_t test_vzip_u32(uint32x2_t a, uint32x2_t b) {
- return vzip_u32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_f32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META129:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x i32> <i32 0, i32 2>
-// CHECK-NEXT: store <2 x float> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META129]]
-// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <2 x float>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x i32> <i32 1, i32 3>
-// CHECK-NEXT: store <2 x float> [[VZIP1_I]], ptr [[TMP6]], align 4, !alias.scope [[META129]]
-// CHECK-NEXT: ret void
-//
-float32x2x2_t test_vzip_f32(float32x2_t a, float32x2_t b) {
- return vzip_f32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_p8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META132]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META132]]
-// CHECK-NEXT: ret void
-//
-poly8x8x2_t test_vzip_p8(poly8x8_t a, poly8x8_t b) {
- return vzip_p8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzip_p16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META135:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META135]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <4 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META135]]
-// CHECK-NEXT: ret void
-//
-poly16x4x2_t test_vzip_p16(poly16x4_t a, poly16x4_t b) {
- return vzip_p16(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_s8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META138:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-// CHECK-NEXT: store <16 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META138]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-// CHECK-NEXT: store <16 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META138]]
-// CHECK-NEXT: ret void
-//
-int8x16x2_t test_vzipq_s8(int8x16_t a, int8x16_t b) {
- return vzipq_s8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_s16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META141:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META141]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <8 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META141]]
-// CHECK-NEXT: ret void
-//
-int16x8x2_t test_vzipq_s16(int16x8_t a, int16x8_t b) {
- return vzipq_s16(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_s32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META144:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x i32> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META144]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <4 x i32>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x i32> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META144]]
-// CHECK-NEXT: ret void
-//
-int32x4x2_t test_vzipq_s32(int32x4_t a, int32x4_t b) {
- return vzipq_s32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_u8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META147:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-// CHECK-NEXT: store <16 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META147]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-// CHECK-NEXT: store <16 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META147]]
-// CHECK-NEXT: ret void
-//
-uint8x16x2_t test_vzipq_u8(uint8x16_t a, uint8x16_t b) {
- return vzipq_u8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_u16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META150:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META150]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <8 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META150]]
-// CHECK-NEXT: ret void
-//
-uint16x8x2_t test_vzipq_u16(uint16x8_t a, uint16x8_t b) {
- return vzipq_u16(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_u32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META153:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x i32> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META153]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <4 x i32>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x i32> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META153]]
-// CHECK-NEXT: ret void
-//
-uint32x4x2_t test_vzipq_u32(uint32x4_t a, uint32x4_t b) {
- return vzipq_u32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_f32(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META156:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>
-// CHECK-NEXT: store <4 x float> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META156]]
-// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <4 x float>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> <i32 2, i32 6, i32 3, i32 7>
-// CHECK-NEXT: store <4 x float> [[VZIP1_I]], ptr [[TMP6]], align 4, !alias.scope [[META156]]
-// CHECK-NEXT: ret void
-//
-float32x4x2_t test_vzipq_f32(float32x4_t a, float32x4_t b) {
- return vzipq_f32(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_p8(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META159:![0-9]+]])
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-// CHECK-NEXT: store <16 x i8> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META159]]
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-// CHECK-NEXT: store <16 x i8> [[VZIP1_I]], ptr [[TMP0]], align 4, !alias.scope [[META159]]
-// CHECK-NEXT: ret void
-//
-poly8x16x2_t test_vzipq_p8(poly8x16_t a, poly8x16_t b) {
- return vzipq_p8(a, b);
-}
-
-// CHECK-LABEL: define void @test_vzipq_p16(
-// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META162:![0-9]+]])
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VZIP_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
-// CHECK-NEXT: store <8 x i16> [[VZIP_I]], ptr [[AGG_RESULT]], align 4, !alias.scope [[META162]]
-// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <8 x i16>, ptr [[AGG_RESULT]], i32 1
-// CHECK-NEXT: [[VZIP1_I:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
-// CHECK-NEXT: store <8 x i16> [[VZIP1_I]], ptr [[TMP4]], align 4, !alias.scope [[META162]]
-// CHECK-NEXT: ret void
-//
-poly16x8x2_t test_vzipq_p16(poly16x8_t a, poly16x8_t b) {
- return vzipq_p16(a, b);
-}
//.
// CHECK: [[META3]] = !{[[META4:![0-9]+]]}
// CHECK: [[META4]] = distinct !{[[META4]], [[META5:![0-9]+]], !"vtrn_s8: %agg.result"}
@@ -27253,58 +26931,4 @@ poly16x8x2_t test_vzipq_p16(poly16x8_t a, poly16x8_t b) {
// CHECK: [[META108]] = !{[[META109:![0-9]+]]}
// CHECK: [[META109]] = distinct !{[[META109]], [[META110:![0-9]+]], !"vuzpq_p16: %agg.result"}
// CHECK: [[META110]] = distinct !{[[META110]], !"vuzpq_p16"}
-// CHECK: [[META111]] = !{[[META112:![0-9]+]]}
-// CHECK: [[META112]] = distinct !{[[META112]], [[META113:![0-9]+]], !"vzip_s8: %agg.result"}
-// CHECK: [[META113]] = distinct !{[[META113]], !"vzip_s8"}
-// CHECK: [[META114]] = !{[[META115:![0-9]+]]}
-// CHECK: [[META115]] = distinct !{[[META115]], [[META116:![0-9]+]], !"vzip_s16: %agg.result"}
-// CHECK: [[META116]] = distinct !{[[META116]], !"vzip_s16"}
-// CHECK: [[META117]] = !{[[META118:![0-9]+]]}
-// CHECK: [[META118]] = distinct !{[[META118]], [[META119:![0-9]+]], !"vzip_s32: %agg.result"}
-// CHECK: [[META119]] = distinct !{[[META119]], !"vzip_s32"}
-// CHECK: [[META120]] = !{[[META121:![0-9]+]]}
-// CHECK: [[META121]] = distinct !{[[META121]], [[META122:![0-9]+]], !"vzip_u8: %agg.result"}
-// CHECK: [[META122]] = distinct !{[[META122]], !"vzip_u8"}
-// CHECK: [[META123]] = !{[[META124:![0-9]+]]}
-// CHECK: [[META124]] = distinct !{[[META124]], [[META125:![0-9]+]], !"vzip_u16: %agg.result"}
-// CHECK: [[META125]] = distinct !{[[META125]], !"vzip_u16"}
-// CHECK: [[META126]] = !{[[META127:![0-9]+]]}
-// CHECK: [[META127]] = distinct !{[[META127]], [[META128:![0-9]+]], !"vzip_u32: %agg.result"}
-// CHECK: [[META128]] = distinct !{[[META128]], !"vzip_u32"}
-// CHECK: [[META129]] = !{[[META130:![0-9]+]]}
-// CHECK: [[META130]] = distinct !{[[META130]], [[META131:![0-9]+]], !"vzip_f32: %agg.result"}
-// CHECK: [[META131]] = distinct !{[[META131]], !"vzip_f32"}
-// CHECK: [[META132]] = !{[[META133:![0-9]+]]}
-// CHECK: [[META133]] = distinct !{[[META133]], [[META134:![0-9]+]], !"vzip_p8: %agg.result"}
-// CHECK: [[META134]] = distinct !{[[META134]], !"vzip_p8"}
-// CHECK: [[META135]] = !{[[META136:![0-9]+]]}
-// CHECK: [[META136]] = distinct !{[[META136]], [[META137:![0-9]+]], !"vzip_p16: %agg.result"}
-// CHECK: [[META137]] = distinct !{[[META137]], !"vzip_p16"}
-// CHECK: [[META138]] = !{[[META139:![0-9]+]]}
-// CHECK: [[META139]] = distinct !{[[META139]], [[META140:![0-9]+]], !"vzipq_s8: %agg.result"}
-// CHECK: [[META140]] = distinct !{[[META140]], !"vzipq_s8"}
-// CHECK: [[META141]] = !{[[META142:![0-9]+]]}
-// CHECK: [[META142]] = distinct !{[[META142]], [[META143:![0-9]+]], !"vzipq_s16: %agg.result"}
-// CHECK: [[META143]] = distinct !{[[META143]], !"vzipq_s16"}
-// CHECK: [[META144]] = !{[[META145:![0-9]+]]}
-// CHECK: [[META145]] = distinct !{[[META145]], [[META146:![0-9]+]], !"vzipq_s32: %agg.result"}
-// CHECK: [[META146]] = distinct !{[[META146]], !"vzipq_s32"}
-// CHECK: [[META147]] = !{[[META148:![0-9]+]]}
-// CHECK: [[META148]] = distinct !{[[META148]], [[META149:![0-9]+]], !"vzipq_u8: %agg.result"}
-// CHECK: [[META149]] = distinct !{[[META149]], !"vzipq_u8"}
-// CHECK: [[META150]] = !{[[META151:![0-9]+]]}
-// CHECK: [[META151]] = distinct !{[[META151]], [[META152:![0-9]+]], !"vzipq_u16: %agg.result"}
-// CHECK: [[META152]] = distinct !{[[META152]], !"vzipq_u16"}
-// CHECK: [[META153]] = !{[[META154:![0-9]+]]}
-// CHECK: [[META154]] = distinct !{[[META154]], [[META155:![0-9]+]], !"vzipq_u32: %agg.result"}
-// CHECK: [[META155]] = distinct !{[[META155]], !"vzipq_u32"}
-// CHECK: [[META156]] = !{[[META157:![0-9]+]]}
-// CHECK: [[META157]] = distinct !{[[META157]], [[META158:![0-9]+]], !"vzipq_f32: %agg.result"}
-// CHECK: [[META158]] = distinct !{[[META158]], !"vzipq_f32"}
-// CHECK: [[META159]] = !{[[META160:![0-9]+]]}
-// CHECK: [[META160]] = distinct !{[[META160]], [[META161:![0-9]+]], !"vzipq_p8: %agg.result"}
-// CHECK: [[META161]] = distinct !{[[META161]], !"vzipq_p8"}
-// CHECK: [[META162]] = !{[[META163:![0-9]+]]}
-// CHECK: [[META163]] = distinct !{[[META163]], [[META164:![0-9]+]], !"vzipq_p16: %agg.result"}
-// CHECK: [[META164]] = distinct !{[[META164]], !"vzipq_p16"}
//.
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