[clang] 53a33fa - Add missing comment (#193050)

[via cfe-commits]

Author: Andrzej Warzyński
Date: 2026-04-21T17:03:03+01:00
New Revision: 53a33fa6ec9a9d7c1345907f4caf01f26e86d79e

URL: https://github.com/llvm/llvm-project/commit/53a33fa6ec9a9d7c1345907f4caf01f26e86d79e
DIFF: https://github.com/llvm/llvm-project/commit/53a33fa6ec9a9d7c1345907f4caf01f26e86d79e.diff

LOG: Add missing comment (#193050)

Added: 
    

Modified: 
    clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

Removed: 
    


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diff  --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index a24e3677ce782..f66bff2c97fa1 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2657,6 +2657,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
   case NEON::BI__builtin_neon_vrsra_n_v:
   case NEON::BI__builtin_neon_vrsraq_n_v: {
     intrName = usgn ? "aarch64.neon.urshl" : "aarch64.neon.srshl";
+    // The llvm intrinsic is expecting negative shift amount for right shift.
+    // Thus we have to make shift amount vec type to be signed.
     cir::VectorType shiftAmtVecTy =
         usgn ? getSignChangedVectorType(builder, ty) : ty;
     llvm::SmallVector<mlir::Value, 2> tmpOps = {ops[1], ops[2]};