[clang] [clang][riscv] Add tests for __builtin_reduce_X support (PR #193082)

[via cfe-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Philip Reames (preames)

<details>
<summary>Changes</summary>

It turns out we already support use of the __builtin_reduce_ family of builtins on the builtin RVV types, but we have no test coverage which demonstrates this.

Note that __builtin_reduce_mul is a bit of a cornercase as currently the clang part works just fine, but the lowering will crash since we don't have a vredprod-esq instruction.

---
Full diff: https://github.com/llvm/llvm-project/pull/193082.diff


1 Files Affected:

- (added) clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c (+156) 


``````````diff
diff --git a/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c b/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
new file mode 100644
index 0000000000000..ac90d4ea5c8a7
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
@@ -0,0 +1,156 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v \
+// RUN: -disable-O0-optnone \
+// RUN:  -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -disable-O0-optnone \
+// RUN:  -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s
+
+// REQUIRES: riscv-registered-target
+
+#include <riscv_vector.h>
+
+// Integer reductions — signed
+
+// CHECK-LABEL: @reduce_add_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_ADD:%.*]] = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_ADD]]
+//
+int reduce_add_i32(vint32m1_t a) {
+  return __builtin_reduce_add(a);
+}
+
+// CHECK-LABEL: @reduce_and_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_AND:%.*]] = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_AND]]
+//
+int reduce_and_i32(vint32m1_t a) {
+  return __builtin_reduce_and(a);
+}
+
+// CHECK-LABEL: @reduce_or_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_OR:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_OR]]
+//
+int reduce_or_i32(vint32m1_t a) {
+  return __builtin_reduce_or(a);
+}
+
+// CHECK-LABEL: @reduce_xor_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_XOR:%.*]] = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_XOR]]
+//
+int reduce_xor_i32(vint32m1_t a) {
+  return __builtin_reduce_xor(a);
+}
+
+// CHECK-LABEL: @reduce_smax_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_MIN]]
+//
+int reduce_smax_i32(vint32m1_t a) {
+  return __builtin_reduce_max(a);
+}
+
+// CHECK-LABEL: @reduce_smin_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_MIN]]
+//
+int reduce_smin_i32(vint32m1_t a) {
+  return __builtin_reduce_min(a);
+}
+
+// Integer reductions — unsigned
+
+// CHECK-LABEL: @reduce_umax_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_MIN]]
+//
+unsigned reduce_umax_u32(vuint32m1_t a) {
+  return __builtin_reduce_max(a);
+}
+
+// CHECK-LABEL: @reduce_umin_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_MIN]]
+//
+unsigned reduce_umin_u32(vuint32m1_t a) {
+  return __builtin_reduce_min(a);
+}
+
+// Floating point reductions
+
+// CHECK-LABEL: @reduce_fmax_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> [[A:%.*]])
+// CHECK-NEXT:    ret float [[RDX_MIN]]
+//
+float reduce_fmax_f32(vfloat32m1_t a) {
+  return __builtin_reduce_max(a);
+}
+
+// CHECK-LABEL: @reduce_fmin_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MIN:%.*]] = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> [[A:%.*]])
+// CHECK-NEXT:    ret float [[RDX_MIN]]
+//
+float reduce_fmin_f32(vfloat32m1_t a) {
+  return __builtin_reduce_min(a);
+}
+
+// CHECK-LABEL: @reduce_fmaximum_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MAXIMUM:%.*]] = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> [[A:%.*]])
+// CHECK-NEXT:    ret float [[RDX_MAXIMUM]]
+//
+float reduce_fmaximum_f32(vfloat32m1_t a) {
+  return __builtin_reduce_maximum(a);
+}
+
+// CHECK-LABEL: @reduce_fminimum_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MINIMUM:%.*]] = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> [[A:%.*]])
+// CHECK-NEXT:    ret float [[RDX_MINIMUM]]
+//
+float reduce_fminimum_f32(vfloat32m1_t a) {
+  return __builtin_reduce_minimum(a);
+}
+
+// Different LMUL
+
+// CHECK-LABEL: @reduce_add_i32_m8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_ADD:%.*]] = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_ADD]]
+//
+int reduce_add_i32_m8(vint32m8_t a) {
+  return __builtin_reduce_add(a);
+}
+
+// Different element width
+
+// CHECK-LABEL: @reduce_add_i64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_ADD:%.*]] = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> [[A:%.*]])
+// CHECK-NEXT:    ret i64 [[RDX_ADD]]
+//
+long long reduce_add_i64(vint64m1_t a) {
+  return __builtin_reduce_add(a);
+}
+
+// CHECK-LABEL: @reduce_mul_i32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[RDX_MUL:%.*]] = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret i32 [[RDX_MUL]]
+//
+int reduce_mul_i32(vint32m1_t a) {
+  return __builtin_reduce_mul(a);
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/193082