[clang] [Clang][AArch64] Lower NEON fcvtz{u/s} intrinsics into fpto{u/s}i.sat (PR #191365)

[Valeriy Savchenko via cfe-commits]

SavchenkoValeriy wrote:

> This feels potentially unsafe from a floating-point exceptions point of view. I know support can be sketchy and I didn't spot a definitely answer within the ACLE, but for SVE there is https://github.com/ARM-software/acle/blob/main/main/acle.md#faults-and-exceptions-in-sve-intrinsics which seems generally applicable.
> 
> As a specific example, the LLVM intrinsics will silently round NaN to zero, whereas the Neon intrinsic probably shouldn't, at least not in all environments. I'm wondering if instead it would be better to add something to AArch64TTIImpl::instCombineIntrinsic that simplifies the Neon intrinsic to an LLVM one when strict fp is not enabled?
> 
> I suspect we already lower some FP operations to stock IR, but I'd rather not follow that path if it is indeed a mistake, and given the code is already here there's no down side to keeping it?

Hey @paulwalker-arm, thanks for bringing this up to my attention!
Both `aarch64.neon.fcvtzs` and `fptosi.sat` have `IntrNoMem` and nothing about strict fp. And maybe you brought up SVE as an example, but just to be sure - I'm not lowering corresponding SVE intrinsics (while those also don't model exceptions). Am I missing something?

https://github.com/llvm/llvm-project/pull/191365