[clang] [CIR] add vsqrt and vsqrtq support (PR #192282)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Apr 17 09:53:24 PDT 2026
https://github.com/Kouunnn updated https://github.com/llvm/llvm-project/pull/192282
>From 5ec81800e2ceec6dd6821735982659ec744ce628 Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile99 at gmail.com>
Date: Tue, 14 Apr 2026 15:37:16 +0800
Subject: [PATCH 1/2] [CIR] add vsqrt and vsqrtq support
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 75dd19d880444..c5fcc06f50092 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2571,8 +2571,17 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vpminnm_v:
case NEON::BI__builtin_neon_vpminnmq_v:
case NEON::BI__builtin_neon_vsqrth_f16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vsqrt_v:
- case NEON::BI__builtin_neon_vsqrtq_v:
+ case NEON::BI__builtin_neon_vsqrtq_v: {
+ // TODO: implement vsqrt and vsqrtq
+ // refer:
+ // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#square-root
+ return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc);
+ }
case NEON::BI__builtin_neon_vrbit_v:
case NEON::BI__builtin_neon_vrbitq_v:
case NEON::BI__builtin_neon_vmaxv_f16:
>From 5f933cbe70294404201fa8f1f34becc9d7ea8ef2 Mon Sep 17 00:00:00 2001
From: ZCkouun <1765074320 at qq.com>
Date: Fri, 17 Apr 2026 17:14:39 +0800
Subject: [PATCH 2/2] [CIR] Add vsqrt/vsqrtq NEON tests
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 6 +-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 14 +---
clang/test/CodeGen/AArch64/neon/vsqrt.c | 67 +++++++++++++++++++
3 files changed, 69 insertions(+), 18 deletions(-)
create mode 100644 clang/test/CodeGen/AArch64/neon/vsqrt.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index c5fcc06f50092..ddc4cb45d955e 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2576,12 +2576,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vsqrt_v:
- case NEON::BI__builtin_neon_vsqrtq_v: {
- // TODO: implement vsqrt and vsqrtq
- // refer:
- // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#square-root
+ case NEON::BI__builtin_neon_vsqrtq_v:
return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc);
- }
case NEON::BI__builtin_neon_vrbit_v:
case NEON::BI__builtin_neon_vrbitq_v:
case NEON::BI__builtin_neon_vmaxv_f16:
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 82a10b626c223..a22ea7d78b8fa 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -21532,19 +21532,7 @@ float64x1_t test_vrecpe_f64(float64x1_t a) {
return vrecpe_f64(a);
}
-// CHECK-LABEL: define dso_local <1 x double> @test_vsqrt_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64
-// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[VSQRT_I:%.*]] = call <1 x double> @llvm.sqrt.v1f64(<1 x double> [[TMP2]])
-// CHECK-NEXT: ret <1 x double> [[VSQRT_I]]
-//
-float64x1_t test_vsqrt_f64(float64x1_t a) {
- return vsqrt_f64(a);
-}
+
// CHECK-LABEL: define dso_local <1 x double> @test_vrecps_f64(
// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
diff --git a/clang/test/CodeGen/AArch64/neon/vsqrt.c b/clang/test/CodeGen/AArch64/neon/vsqrt.c
new file mode 100644
index 0000000000000..0b6330ccaf940
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/vsqrt.c
@@ -0,0 +1,67 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+#include <arm_neon.h>
+
+//===----------------------------------------------------------------------===//
+// 2.1.1.11. Square root
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#square-root
+//===----------------------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vsqrt_f32(
+// CIR-LABEL: @vsqrt_f32(
+float32x2_t test_vsqrt_f32(float32x2_t a) {
+// CIR: cir.call_llvm_intrinsic "sqrt" %{{.*}} : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// LLVM: [[TMP2:%.*]] = bitcast <2 x float> [[TMP0]] to <2 x i32>
+// LLVM-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>
+// LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>
+// LLVM-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[TMP4]])
+// LLVM-NEXT: ret <2 x float> [[TMP5]]
+ return vsqrt_f32(a);
+}
+
+// LLVM-LABEL: @test_vsqrtq_f32(
+// CIR-LABEL: @vsqrtq_f32(
+float32x4_t test_vsqrtq_f32(float32x4_t a) {
+// CIR: cir.call_llvm_intrinsic "sqrt" %{{.*}} : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> noundef [[TMP0:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP2:%.*]] = bitcast <4 x float> [[TMP0]] to <4 x i32>
+// LLVM-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>
+// LLVM-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>
+// LLVM-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP4]])
+// LLVM-NEXT: ret <4 x float> [[TMP5]]
+ return vsqrtq_f32(a);
+}
+
+// LLVM-LABEL: @test_vsqrt_f64(
+// CIR-LABEL: @vsqrt_f64(
+float64x1_t test_vsqrt_f64(float64x1_t a) {
+// CIR: cir.call_llvm_intrinsic "sqrt" %{{.*}} : (!cir.vector<1 x !cir.double>) -> !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> noundef [[TMP0:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP2:%.*]] = bitcast <1 x double> [[TMP0]] to i64
+// LLVM-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0
+// LLVM-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[DOTSROA_0_0_VEC_INSERT]] to <8 x i8>
+// LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
+// LLVM-NEXT: [[TMP5:%.*]] = call <1 x double> @llvm.sqrt.v1f64(<1 x double> [[TMP4]])
+// LLVM-NEXT: ret <1 x double> [[TMP5]]
+ return vsqrt_f64(a);
+}
+
+// LLVM-LABEL: @test_vsqrtq_f64(
+// CIR-LABEL: @vsqrtq_f64(
+float64x2_t test_vsqrtq_f64(float64x2_t a) {
+// CIR: cir.call_llvm_intrinsic "sqrt" %{{.*}} : (!cir.vector<2 x !cir.double>) -> !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> noundef [[TMP0:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP2:%.*]] = bitcast <2 x double> [[TMP0]] to <2 x i64>
+// LLVM-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
+// LLVM-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
+// LLVM-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP4]])
+// LLVM-NEXT: ret <2 x double> [[TMP5]]
+ return vsqrtq_f64(a);
+}
More information about the cfe-commits
mailing list