[clang] c486538 - [PowerPC] Implement Elliptic Curve Cryptography Builtins (#184681)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 15 10:41:11 PDT 2026
Author: Lei Huang
Date: 2026-04-15T13:41:05-04:00
New Revision: c4865380622f229188f29ef23d09eb3a564762ca
URL: https://github.com/llvm/llvm-project/commit/c4865380622f229188f29ef23d09eb3a564762ca
DIFF: https://github.com/llvm/llvm-project/commit/c4865380622f229188f29ef23d09eb3a564762ca.diff
LOG: [PowerPC] Implement Elliptic Curve Cryptography Builtins (#184681)
Add support for the following ISA Future elliptic curve cryptograpy
builtins.
* Builtins with immediate parameters:
vector unsigned char __builtin_xxmulmul(vector unsigned char, vector
unsigned char, unsigned int);
vector unsigned char __builtin_xxmulmulhiadd(vector unsigned char,
vector unsigned char, unsigned int, unsigned int, unsigned int); vector
unsigned char __builtin_xxmulmulloadd(vector unsigned char, vector
unsigned char, unsigned int, unsigned int); vector unsigned char
__builtin_xxssumudm(vector unsigned char, vector unsigned char, unsigned
int);
vector unsigned char __builtin_xxssumudmc(vector unsigned char, vector
unsigned char, unsigned int);
vector unsigned char __builtin_xxssumudmcext(vector unsigned char,
vector unsigned char, vector unsigned char, unsigned int);
* Builtins with two vector parameters (no immediates):
vector unsigned char __builtin_xsaddadduqm(vector unsigned char, vector
unsigned char);
vector unsigned char __builtin_xsaddaddsuqm(vector unsigned char, vector
unsigned char);
vector unsigned char __builtin_xsaddsubuqm(vector unsigned char, vector
unsigned char);
vector unsigned char __builtin_xsaddsubsuqm(vector unsigned char, vector
unsigned char);
vector unsigned char __builtin_xsmerge2t1uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsmerge2t2uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsmerge2t3uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsmerge3t1uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase2t1uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase2t2uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase2t3uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase2t4uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase3t1uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase3t2uqm(vector unsigned char,
vector unsigned char);
vector unsigned char __builtin_xsrebase3t3uqm(vector unsigned char,
vector unsigned char);
Assisted by AI.
Added:
clang/test/CodeGen/PowerPC/builtins-ecc.c
clang/test/Sema/PowerPC/builtins-ecc-error.c
llvm/test/CodeGen/PowerPC/builtins-ecc.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrFuture.td
llvm/lib/Target/PowerPC/PPCInstrP10.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index c0c92c0b73793..8ad7efe5e814d 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -1162,6 +1162,29 @@ UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvf16gerx2, "vW1024*W256V",
UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvf16gerx2, "vW1024*W256Vi255i15i3",
"mma,isa-future-instructions")
+// Elliptic Curve Cryptography Builtins
+UNALIASED_CUSTOM_BUILTIN(xxmulmul, "VVVi7", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xxmulmulhiadd, "VVVi1i1i1", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xxmulmulloadd, "VVVi1i1", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xxssumudm, "VVVi1", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xxssumudmc, "VVVi1", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xxssumudmcext, "VVVVi1", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsaddadduqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsaddaddsuqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsaddsubuqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsaddsubsuqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsmerge2t1uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsmerge2t2uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsmerge2t3uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsmerge3t1uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase2t1uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase2t2uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase2t3uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase2t4uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase3t1uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase3t2uqm, "VVV", false, "future-vector")
+UNALIASED_CUSTOM_BUILTIN(xsrebase3t3uqm, "VVV", false, "future-vector")
+
// FIXME: Obviously incomplete.
#undef BUILTIN
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 30ea714fbb6f8..c9a41df806aff 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -59,6 +59,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasP9Vector = true;
} else if (Feature == "+power10-vector") {
HasP10Vector = true;
+ } else if (Feature == "+future-vector") {
+ HasFutureVector = true;
} else if (Feature == "+pcrelative-memops") {
HasPCRelativeMemops = true;
} else if (Feature == "+spe" || Feature == "+efpu2") {
@@ -434,6 +436,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__POWER10_VECTOR__");
if (HasPCRelativeMemops)
Builder.defineMacro("__PCREL__");
+ if (HasFutureVector)
+ Builder.defineMacro("__FUTURE_VECTOR__");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 6f90ff1f5d57c..a9f49aa3aebe1 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -69,6 +69,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
bool HasFrsqrte = false;
bool HasFrsqrtes = false;
bool HasP10Vector = false;
+ bool HasFutureVector = false;
bool HasPCRelativeMemops = false;
bool HasQuadwordAtomics = false;
bool UseLongCalls = false;
diff --git a/clang/test/CodeGen/PowerPC/builtins-ecc.c b/clang/test/CodeGen/PowerPC/builtins-ecc.c
new file mode 100644
index 0000000000000..cfce1dee64820
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-ecc.c
@@ -0,0 +1,242 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-unknown \
+// RUN: -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown \
+// RUN: -target-cpu future -emit-llvm %s -o - | FileCheck %s
+
+// AI Generated.
+
+vector unsigned char vuca, vucb, vucc;
+
+// CHECK-LABEL: @test_xxmulmul(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmul(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 3)
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xxmulmul() {
+ return __builtin_xxmulmul(vuca, vucb, 3);
+}
+
+// CHECK-LABEL: @test_xxmulmulhiadd(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 0, i32 1, i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xxmulmulhiadd() {
+ return __builtin_xxmulmulhiadd(vuca, vucb, 0, 1, 0);
+}
+
+// CHECK-LABEL: @test_xxmulmulloadd(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 1, i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xxmulmulloadd() {
+ return __builtin_xxmulmulloadd(vuca, vucb, 1, 0);
+}
+
+// CHECK-LABEL: @test_xxssumudm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxssumudm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 1)
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xxssumudm() {
+ return __builtin_xxssumudm(vuca, vucb, 1);
+}
+
+// CHECK-LABEL: @test_xxssumudmc(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 0)
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xxssumudmc() {
+ return __builtin_xxssumudmc(vuca, vucb, 0);
+}
+
+// CHECK-LABEL: @test_xxssumudmcext(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr @vucc, align 16
+// CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]], i32 1)
+// CHECK-NEXT: ret <16 x i8> [[TMP3]]
+//
+vector unsigned char test_xxssumudmcext() {
+ return __builtin_xxssumudmcext(vuca, vucb, vucc, 1);
+}
+
+// CHECK-LABEL: @test_xsaddadduqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsaddadduqm() {
+ return __builtin_xsaddadduqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsaddaddsuqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsaddaddsuqm() {
+ return __builtin_xsaddaddsuqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsaddsubuqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsaddsubuqm() {
+ return __builtin_xsaddsubuqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsaddsubsuqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsaddsubsuqm() {
+ return __builtin_xsaddsubsuqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsmerge2t1uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsmerge2t1uqm() {
+ return __builtin_xsmerge2t1uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsmerge2t2uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsmerge2t2uqm() {
+ return __builtin_xsmerge2t2uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsmerge2t3uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsmerge2t3uqm() {
+ return __builtin_xsmerge2t3uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsmerge3t1uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsmerge3t1uqm() {
+ return __builtin_xsmerge3t1uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase2t1uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase2t1uqm() {
+ return __builtin_xsrebase2t1uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase2t2uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase2t2uqm() {
+ return __builtin_xsrebase2t2uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase2t3uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase2t3uqm() {
+ return __builtin_xsrebase2t3uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase2t4uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase2t4uqm() {
+ return __builtin_xsrebase2t4uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase3t1uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase3t1uqm() {
+ return __builtin_xsrebase3t1uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase3t2uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase3t2uqm() {
+ return __builtin_xsrebase3t2uqm(vuca, vucb);
+}
+
+// CHECK-LABEL: @test_xsrebase3t3uqm(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
+// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
+// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
+// CHECK-NEXT: ret <16 x i8> [[TMP2]]
+//
+vector unsigned char test_xsrebase3t3uqm() {
+ return __builtin_xsrebase3t3uqm(vuca, vucb);
+}
diff --git a/clang/test/Sema/PowerPC/builtins-ecc-error.c b/clang/test/Sema/PowerPC/builtins-ecc-error.c
new file mode 100644
index 0000000000000..e56c7a11017e0
--- /dev/null
+++ b/clang/test/Sema/PowerPC/builtins-ecc-error.c
@@ -0,0 +1,66 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu future \
+// RUN: -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -target-cpu future \
+// RUN: -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN: -fsyntax-only -verify=pwr10 %s
+
+vector unsigned char vuca, vucb, vucc;
+int ia;
+
+void test_xxmulmul() {
+ __builtin_xxmulmul(vuca, vucb, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} \
+ // pwr10-error {{'__builtin_xxmulmul' needs target feature future-vector}}
+ __builtin_xxmulmul(vuca, vucb, -1); // expected-error {{argument value -1 is outside the valid range [0, 7]}} \
+ // pwr10-error {{'__builtin_xxmulmul' needs target feature future-vector}}
+ __builtin_xxmulmul(vuca, vucb, ia); // expected-error {{argument to '__builtin_xxmulmul' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxmulmul' needs target feature future-vector}}
+}
+
+void test_xxmulmulhiadd() {
+ __builtin_xxmulmulhiadd(vuca, vucb, 2, 0, 0); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxmulmulhiadd' needs target feature future-vector}}
+ __builtin_xxmulmulhiadd(vuca, vucb, 0, 2, 0); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxmulmulhiadd' needs target feature future-vector}}
+ __builtin_xxmulmulhiadd(vuca, vucb, 0, 0, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxmulmulhiadd' needs target feature future-vector}}
+ __builtin_xxmulmulhiadd(vuca, vucb, ia, 0, 0); // expected-error {{argument to '__builtin_xxmulmulhiadd' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxmulmulhiadd' needs target feature future-vector}}
+}
+
+void test_xxmulmulloadd() {
+ __builtin_xxmulmulloadd(vuca, vucb, 2, 0); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxmulmulloadd' needs target feature future-vector}}
+ __builtin_xxmulmulloadd(vuca, vucb, 0, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxmulmulloadd' needs target feature future-vector}}
+ __builtin_xxmulmulloadd(vuca, vucb, ia, 0); // expected-error {{argument to '__builtin_xxmulmulloadd' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxmulmulloadd' needs target feature future-vector}}
+}
+
+void test_xxssumudm() {
+ __builtin_xxssumudm(vuca, vucb, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudm' needs target feature future-vector}}
+ __builtin_xxssumudm(vuca, vucb, -1); // expected-error {{argument value -1 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudm' needs target feature future-vector}}
+ __builtin_xxssumudm(vuca, vucb, ia); // expected-error {{argument to '__builtin_xxssumudm' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxssumudm' needs target feature future-vector}}
+}
+
+void test_xxssumudmc() {
+ __builtin_xxssumudmc(vuca, vucb, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudmc' needs target feature future-vector}}
+ __builtin_xxssumudmc(vuca, vucb, -1); // expected-error {{argument value -1 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudmc' needs target feature future-vector}}
+ __builtin_xxssumudmc(vuca, vucb, ia); // expected-error {{argument to '__builtin_xxssumudmc' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxssumudmc' needs target feature future-vector}}
+}
+
+void test_xxssumudmcext() {
+ __builtin_xxssumudmcext(vuca, vucb, vucc, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudmcext' needs target feature future-vector}}
+ __builtin_xxssumudmcext(vuca, vucb, vucc, -1); // expected-error {{argument value -1 is outside the valid range [0, 1]}} \
+ // pwr10-error {{'__builtin_xxssumudmcext' needs target feature future-vector}}
+ __builtin_xxssumudmcext(vuca, vucb, vucc, ia); // expected-error {{argument to '__builtin_xxssumudmcext' must be a constant integer}} \
+ // pwr10-error {{'__builtin_xxssumudmcext' needs target feature future-vector}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 03e9669a137ae..0af95ab0bb78a 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -2196,4 +2196,95 @@ let TargetPrefix = "ppc" in {
DefaultAttrsIntrinsic<[llvm_i64_ty],[llvm_ptr_ty,
llvm_i64_ty, llvm_i64_ty],
[IntrArgMemOnly]>;
+
+ // Elliptic Curve Cryptography Intrinsics
+ def int_ppc_xxmulmul : ClangBuiltin<"__builtin_xxmulmul">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+ def int_ppc_xxmulmulhiadd : ClangBuiltin<"__builtin_xxmulmulhiadd">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty,
+ llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>,
+ ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
+ def int_ppc_xxmulmulloadd : ClangBuiltin<"__builtin_xxmulmulloadd">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty,
+ llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>,
+ ImmArg<ArgIndex<3>>]>;
+ def int_ppc_xxssumudm : ClangBuiltin<"__builtin_xxssumudm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+ def int_ppc_xxssumudmc : ClangBuiltin<"__builtin_xxssumudmc">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+ def int_ppc_xxssumudmcext : ClangBuiltin<"__builtin_xxssumudmcext">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
+ llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_ppc_xsaddadduqm : ClangBuiltin<"__builtin_xsaddadduqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsaddaddsuqm : ClangBuiltin<"__builtin_xsaddaddsuqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsaddsubuqm : ClangBuiltin<"__builtin_xsaddsubuqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsaddsubsuqm : ClangBuiltin<"__builtin_xsaddsubsuqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsmerge2t1uqm : ClangBuiltin<"__builtin_xsmerge2t1uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsmerge2t2uqm : ClangBuiltin<"__builtin_xsmerge2t2uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsmerge2t3uqm : ClangBuiltin<"__builtin_xsmerge2t3uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsmerge3t1uqm : ClangBuiltin<"__builtin_xsmerge3t1uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase2t1uqm : ClangBuiltin<"__builtin_xsrebase2t1uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase2t2uqm : ClangBuiltin<"__builtin_xsrebase2t2uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase2t3uqm : ClangBuiltin<"__builtin_xsrebase2t3uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase2t4uqm : ClangBuiltin<"__builtin_xsrebase2t4uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase3t1uqm : ClangBuiltin<"__builtin_xsrebase3t1uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase3t2uqm : ClangBuiltin<"__builtin_xsrebase3t2uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_xsrebase3t3uqm : ClangBuiltin<"__builtin_xsrebase3t3uqm">,
+ DefaultAttrsIntrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1561624b5e4ce..bd90d7b86c95a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -612,6 +612,50 @@ let Predicates = [HasFutureVector] in {
v4i32:$vB))>;
def : Pat<(v4i32 (int_ppc_altivec_vrlw v4i32:$vA, v4i32:$vB)),
(v4i32 (XVRLW v4i32:$vA, v4i32:$vB))>;
+
+ // Elliptic Curve Cryptography Patterns
+ def : Pat<(v16i8 (int_ppc_xxmulmul v16i8:$XA, v16i8:$XB, u3imm_timm:$S)),
+ (v16i8 (COPY_TO_REGCLASS (XXMULMUL RCCp.AToVSRC, RCCp.BToVSRC, $S), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xxmulmulhiadd v16i8:$XA, v16i8:$XB, u1imm_timm:$S0, u1imm_timm:$S1, u1imm_timm:$S2)),
+ (v16i8 (COPY_TO_REGCLASS (XXMULMULHIADD RCCp.AToVSRC, RCCp.BToVSRC, $S0, $S1, $S2), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xxmulmulloadd v16i8:$XA, v16i8:$XB, u1imm_timm:$S1, u1imm_timm:$S2)),
+ (v16i8 (COPY_TO_REGCLASS (XXMULMULLOADD RCCp.AToVSRC, RCCp.BToVSRC, $S1, $S2), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xxssumudm v16i8:$XA, v16i8:$XB, u1imm_timm:$P)),
+ (v16i8 (COPY_TO_REGCLASS (XXSSUMUDM RCCp.AToVSRC, RCCp.BToVSRC, $P), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xxssumudmc v16i8:$XA, v16i8:$XB, u1imm_timm:$P)),
+ (v16i8 (COPY_TO_REGCLASS (XXSSUMUDMC RCCp.AToVSRC, RCCp.BToVSRC, $P), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xxssumudmcext v16i8:$XA, v16i8:$XB, v16i8:$XC, u1imm_timm:$P)),
+ (v16i8 (COPY_TO_REGCLASS (XXSSUMUDMCEXT RCCp.AToVSRC, RCCp.BToVSRC, RCCp.CToVSRC, $P), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsaddadduqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSADDADDUQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsaddaddsuqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSADDADDSUQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsaddsubuqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSADDSUBUQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsaddsubsuqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSADDSUBSUQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsmerge2t1uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSMERGE2T1UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsmerge2t2uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSMERGE2T2UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsmerge2t3uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSMERGE2T3UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsmerge3t1uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSMERGE3T1UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase2t1uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE2T1UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase2t2uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE2T2UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase2t3uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE2T3UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase2t4uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE2T4UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase3t1uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE3T1UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase3t2uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE3T2UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
+ def : Pat<(v16i8 (int_ppc_xsrebase3t3uqm v16i8:$XA, v16i8:$XB)),
+ (v16i8 (COPY_TO_REGCLASS (XSREBASE3T3UQM RCCp.AToVSRC, RCCp.BToVSRC), VSRC))>;
}
//---------------------------- Instruction aliases ---------------------------//
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index fdea9c5a4e0ba..6799a9838ec63 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -652,6 +652,7 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
def RCCp {
dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
+ dag CToVSRC = (COPY_TO_REGCLASS $XC, VSRC);
}
let Predicates = [PrefixInstrs] in {
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ecc.ll b/llvm/test/CodeGen/PowerPC/builtins-ecc.ll
new file mode 100644
index 0000000000000..abae8c8706eef
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ecc.ll
@@ -0,0 +1,216 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
+
+declare <16 x i8> @llvm.ppc.xxmulmul(<16 x i8>, <16 x i8>, i32 immarg)
+declare <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8>, <16 x i8>, i32 immarg, i32 immarg, i32 immarg)
+declare <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8>, <16 x i8>, i32 immarg, i32 immarg)
+declare <16 x i8> @llvm.ppc.xxssumudm(<16 x i8>, <16 x i8>, i32 immarg)
+declare <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8>, <16 x i8>, i32 immarg)
+declare <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)
+declare <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_xxmulmul(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xxmulmul:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxmulmul vs34, vs34, vs35, 3
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxmulmul(<16 x i8> %a, <16 x i8> %b, i32 3)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xxmulmulhiadd(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xxmulmulhiadd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxmulmulhiadd vs34, vs34, vs35, 0, 1, 0
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xxmulmulloadd(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xxmulmulloadd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxmulmulloadd vs34, vs34, vs35, 1, 0
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xxssumudm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xxssumudm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxssumudm vs34, vs34, vs35, 1
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxssumudm(<16 x i8> %a, <16 x i8> %b, i32 1)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xxssumudmc(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xxssumudmc:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxssumudmc vs34, vs34, vs35, 0
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8> %a, <16 x i8> %b, i32 0)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xxssumudmcext(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: test_xxssumudmcext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xxssumudmcext vs34, vs34, vs35, vs36, 1
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsaddadduqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsaddadduqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsaddadduqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsaddaddsuqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsaddaddsuqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsaddaddsuqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsaddsubuqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsaddsubuqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsaddsubuqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsaddsubsuqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsaddsubsuqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsaddsubsuqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsmerge2t1uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsmerge2t1uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsmerge2t1uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsmerge2t2uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsmerge2t2uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsmerge2t2uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsmerge2t3uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsmerge2t3uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsmerge2t3uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsmerge3t1uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsmerge3t1uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsmerge3t1uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase2t1uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase2t1uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase2t1uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase2t2uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase2t2uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase2t2uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase2t3uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase2t3uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase2t3uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase2t4uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase2t4uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase2t4uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase3t1uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase3t1uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase3t1uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase3t2uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase3t2uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase3t2uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
+
+define <16 x i8> @test_xsrebase3t3uqm(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_xsrebase3t3uqm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xsrebase3t3uqm vs34, vs34, vs35
+; CHECK-NEXT: blr
+ %res = call <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %res
+}
\ No newline at end of file
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