[clang] Support reinterpret cast intrinisc for OFP8 (PR #191626)
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cfe-commits at lists.llvm.org
Sat Apr 11 05:29:39 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Brandon Wu (4vtomat)
<details>
<summary>Changes</summary>
spec: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/433
stacked on: https://github.com/llvm/llvm-project/pull/191349
---
Patch is 849.87 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/191626.diff
23 Files Affected:
- (modified) clang/include/clang/AST/TypeBase.h (+1-1)
- (modified) clang/include/clang/Basic/RISCVVTypes.def (+36)
- (modified) clang/include/clang/Basic/riscv_vector.td (+6)
- (modified) clang/include/clang/Serialization/ASTBitCodes.h (+1-1)
- (modified) clang/lib/Sema/SemaRISCV.cpp (+33-4)
- (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+11-3)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (+80-80)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (+96-96)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (+24-24)
- (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (+260)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (+80-80)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (+96-96)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (+24-24)
- (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (+260)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (+166-166)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (+280-280)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (+48-48)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (+166-166)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (+280-280)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (+48-48)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp (+37-1)
- (modified) clang/test/Sema/riscv-types.c (+44-1)
- (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+9)
``````````diff
diff --git a/clang/include/clang/AST/TypeBase.h b/clang/include/clang/AST/TypeBase.h
index 8802b15d99034..dda91edec14a2 100644
--- a/clang/include/clang/AST/TypeBase.h
+++ b/clang/include/clang/AST/TypeBase.h
@@ -1962,7 +1962,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase {
unsigned : NumTypeBits;
/// The kind (BuiltinType::Kind) of builtin type this is.
- static constexpr unsigned NumOfBuiltinTypeBits = 9;
+ static constexpr unsigned NumOfBuiltinTypeBits = 10;
unsigned Kind : NumOfBuiltinTypeBits;
};
diff --git a/clang/include/clang/Basic/RISCVVTypes.def b/clang/include/clang/Basic/RISCVVTypes.def
index ccb8cb39068e2..19448e6bf9c43 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -73,6 +73,11 @@
RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false, true)
#endif
+#ifndef RVV_VECTOR_TYPE_OFP8
+#define RVV_VECTOR_TYPE_OFP8(Name, Id, SingletonId, NumEls, E5m2) \
+ RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, 8, 1, false)
+#endif
+
//===- Vector types -------------------------------------------------------===//
RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t", RvvInt8mf8, RvvInt8mf8Ty, 1, 8, 1, true)
@@ -127,6 +132,36 @@ RVV_VECTOR_TYPE_INT("__rvv_uint64m2_t",RvvUint64m2,RvvUint64m2Ty,2, 64, 1, fals
RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4, 64, 1, false)
RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8, 64, 1, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3mf8_t", RvvFloat8E4M3mf8,
+ RvvFloat8E4M3mf8Ty, 1, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3mf4_t", RvvFloat8E4M3mf4,
+ RvvFloat8E4M3mf4Ty, 2, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3mf2_t", RvvFloat8E4M3mf2,
+ RvvFloat8E4M3mf2Ty, 4, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3m1_t", RvvFloat8E4M3m1,
+ RvvFloat8E4M3m1Ty, 8, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3m2_t", RvvFloat8E4M3m2,
+ RvvFloat8E4M3m2Ty, 16, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3m4_t", RvvFloat8E4M3m4,
+ RvvFloat8E4M3m4Ty, 32, false)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e4m3m8_t", RvvFloat8E4M3m8,
+ RvvFloat8E4M3m8Ty, 64, false)
+
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2mf8_t", RvvFloat8E5M2mf8,
+ RvvFloat8E5M2mf8Ty, 1, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2mf4_t", RvvFloat8E5M2mf4,
+ RvvFloat8E5M2mf4Ty, 2, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2mf2_t", RvvFloat8E5M2mf2,
+ RvvFloat8E5M2mf2Ty, 4, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2m1_t", RvvFloat8E5M2m1,
+ RvvFloat8E5M2m1Ty, 8, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2m2_t", RvvFloat8E5M2m2,
+ RvvFloat8E5M2m2Ty, 16, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2m4_t", RvvFloat8E5M2m4,
+ RvvFloat8E5M2m4Ty, 32, true)
+RVV_VECTOR_TYPE_OFP8("__rvv_float8e5m2m8_t", RvvFloat8E5M2m8,
+ RvvFloat8E5M2m8Ty, 64, true)
+
RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1, 16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2, 16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4, 16, 1)
@@ -508,6 +543,7 @@ RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m2x4_t", RvvBFloat16m2x4, RvvBFloat16m2x4T
RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16m4x2_t", RvvBFloat16m4x2, RvvBFloat16m4x2Ty,
16, 16, 2)
+#undef RVV_VECTOR_TYPE_OFP8
#undef RVV_VECTOR_TYPE_BFLOAT
#undef RVV_VECTOR_TYPE_FLOAT
#undef RVV_VECTOR_TYPE_INT
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 5e4edbe01f1cd..4e258aa82995a 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1805,6 +1805,12 @@ let HasMasked = false, HasVL = false, IRName = "" in {
def vreinterpret_u_bf16 : RVVBuiltin<"vUv", "Uvv", "y", "Uv">;
def vreinterpret_bf16_i : RVVBuiltin<"Ivv", "vIv", "y", "v">;
def vreinterpret_bf16_u : RVVBuiltin<"Uvv", "vUv", "y", "v">;
+ let RequiredFeatures = ["zvfofp8min"] in {
+ def vreinterpret_u_f8e4m3 : RVVBuiltin<"vUv", "Uvv", "a", "Uv">;
+ def vreinterpret_f8e4m3_u : RVVBuiltin<"Uvv", "vUv", "a", "v">;
+ def vreinterpret_u_f8e5m2 : RVVBuiltin<"vUv", "Uvv", "b", "Uv">;
+ def vreinterpret_f8e5m2_u : RVVBuiltin<"Uvv", "vUv", "b", "v">;
+ }
// Reinterpret between different SEW under the same LMUL
foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)",
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h
index 783cd82895a90..b8c57636779ce 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1166,7 +1166,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 515;
+const unsigned NUM_PREDEF_TYPE_IDS = 529;
// Ensure we do not overrun the predefined types we reserved
// in the enum PredefinedTypeIDs above.
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3cf5a0963b39c..396c1f0ec12c3 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -137,9 +137,24 @@ static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) {
QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), false);
break;
case ScalarTypeKind::FloatE4M3:
- case ScalarTypeKind::FloatE5M2:
- QT = Context.getIntTypeForBitwidth(8, false);
- break;
+ case ScalarTypeKind::FloatE5M2: {
+ // TODO: This is a workaround code to only support OP8 RVV types without
+ // supporting scalar OFP8 types. We need to refactor after scalar types are
+ // supported.
+ assert(Type->isVector() && "Only support vector of OFP8 types.");
+ bool IsE5M2 = Type->getScalarType() == ScalarTypeKind::FloatE5M2;
+ unsigned Scale = *Type->getScale();
+#define RVV_VECTOR_TYPE_OFP8(Name, Id, SingletonId, NumEls, E5m2) \
+ if (IsE5M2 == E5m2 && Scale == NumEls) \
+ QT = Context.SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
+ assert(!QT.isNull() && "Unsupported OFP8 vector type");
+ if (Type->isConstant())
+ QT = Context.getConstType(QT);
+ if (Type->isPointer())
+ QT = Context.getPointerType(QT);
+ return QT;
+ }
case ScalarTypeKind::BFloat:
QT = Context.BFloat16Ty;
break;
@@ -1513,11 +1528,23 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
void SemaRISCV::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
const llvm::StringMap<bool> &FeatureMap) {
+ const BuiltinType *BT = Ty->castAs<BuiltinType>();
ASTContext::BuiltinVectorTypeInfo Info =
- SemaRef.Context.getBuiltinVectorTypeInfo(Ty->castAs<BuiltinType>());
+ SemaRef.Context.getBuiltinVectorTypeInfo(BT);
unsigned EltSize = SemaRef.Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ auto IsOFP8Type = [&]() {
+ switch (BT->getKind()) {
+#define RVV_VECTOR_TYPE_OFP8(Name, Id, SingletonId, NumEls, E5m2) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
+ return true;
+ default:
+ return false;
+ }
+ };
+
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
!FeatureMap.lookup("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve64d";
@@ -1554,6 +1581,8 @@ void SemaRISCV::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!FeatureMap.lookup("zve32x"))
Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zve32x";
+ else if (IsOFP8Type() && !FeatureMap.lookup("experimental-zvfofp8min"))
+ Diag(Loc, diag::err_riscv_type_requires_extension) << Ty << "zvfofp8min";
}
/// Are the two types RVV-bitcast-compatible types? I.e. is bitcasting from the
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 218d7b75ff7f2..e2227132be8df 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -250,10 +250,14 @@ void RVVType::initClangBuiltinStr() {
ClangBuiltinStr += "int";
break;
case ScalarTypeKind::UnsignedInteger:
- case ScalarTypeKind::FloatE4M3:
- case ScalarTypeKind::FloatE5M2:
ClangBuiltinStr += "uint";
break;
+ case ScalarTypeKind::FloatE4M3:
+ ClangBuiltinStr += "float8e4m3" + LMUL.str() + "_t";
+ return;
+ case ScalarTypeKind::FloatE5M2:
+ ClangBuiltinStr += "float8e5m2" + LMUL.str() + "_t";
+ return;
default:
llvm_unreachable("ScalarTypeKind is invalid");
}
@@ -327,9 +331,13 @@ void RVVType::initTypeStr() {
Str += getTypeString("int");
break;
case ScalarTypeKind::UnsignedInteger:
+ Str += getTypeString("uint");
+ break;
case ScalarTypeKind::FloatE4M3:
+ Str += Twine("vfloat8e4m3" + LMUL.str() + "_t").str();
+ break;
case ScalarTypeKind::FloatE5M2:
- Str += getTypeString("uint");
+ Str += Twine("vfloat8e5m2" + LMUL.str() + "_t").str();
break;
default:
llvm_unreachable("ScalarType is invalid!");
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
index 3daae3806afdf..ec8b8c0f9c1e5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
@@ -13,7 +13,7 @@
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
-vuint8mf8_t test_vfncvt_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
+vfloat8e4m3mf8_t test_vfncvt_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf8(vs2, vl);
}
@@ -23,7 +23,7 @@ vuint8mf8_t test_vfncvt_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
-vuint8mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
+vfloat8e4m3mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf8(vs2, vl);
}
@@ -33,7 +33,7 @@ vuint8mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vfncvt_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
+vfloat8e4m3mf4_t test_vfncvt_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf4(vs2, vl);
}
@@ -43,7 +43,7 @@ vuint8mf4_t test_vfncvt_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
+vfloat8e4m3mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf4(vs2, vl);
}
@@ -53,7 +53,7 @@ vuint8mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vfncvt_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
+vfloat8e4m3mf2_t test_vfncvt_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf2(vs2, vl);
}
@@ -63,7 +63,7 @@ vuint8mf2_t test_vfncvt_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
+vfloat8e4m3mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf2(vs2, vl);
}
@@ -73,7 +73,7 @@ vuint8mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vfncvt_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
+vfloat8e4m3m1_t test_vfncvt_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3m1(vs2, vl);
}
@@ -83,7 +83,7 @@ vuint8m1_t test_vfncvt_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vfncvt_sat_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
+vfloat8e4m3m1_t test_vfncvt_sat_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3m1(vs2, vl);
}
@@ -93,7 +93,7 @@ vuint8m1_t test_vfncvt_sat_f_f_q_f8e4m3m1(vfloat32m4_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vfncvt_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
+vfloat8e4m3m2_t test_vfncvt_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3m2(vs2, vl);
}
@@ -103,7 +103,7 @@ vuint8m2_t test_vfncvt_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vfncvt_sat_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
+vfloat8e4m3m2_t test_vfncvt_sat_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3m2(vs2, vl);
}
@@ -113,7 +113,7 @@ vuint8m2_t test_vfncvt_sat_f_f_q_f8e4m3m2(vfloat32m8_t vs2, size_t vl) {
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
-vuint8mf8_t test_vfncvt_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
+vfloat8e4m3mf8_t test_vfncvt_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf8_m(vm, vs2, vl);
}
@@ -124,7 +124,7 @@ vuint8mf8_t test_vfncvt_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
-vuint8mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
+vfloat8e4m3mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf8_m(vm, vs2, vl);
}
@@ -135,7 +135,7 @@ vuint8mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8_m(vbool64_t vm, vfloat32mf2_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vfncvt_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
+vfloat8e4m3mf4_t test_vfncvt_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf4_m(vm, vs2, vl);
}
@@ -146,7 +146,7 @@ vuint8mf4_t test_vfncvt_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
+vfloat8e4m3mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf4_m(vm, vs2, vl);
}
@@ -157,7 +157,7 @@ vuint8mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4_m(vbool32_t vm, vfloat32m1_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vfncvt_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
+vfloat8e4m3mf2_t test_vfncvt_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3mf2_m(vm, vs2, vl);
}
@@ -168,7 +168,7 @@ vuint8mf2_t test_vfncvt_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
+vfloat8e4m3mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
size_t vl) {
return __riscv_vfncvt_sat_f_f_q_f8e4m3mf2_m(vm, vs2, vl);
}
@@ -179,7 +179,7 @@ vuint8mf2_t test_vfncvt_sat_f_f_q_f8e4m3mf2_m(vbool16_t vm, vfloat32m2_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vfncvt_f_f_q_f8e4m3m1_m(vbool8_t vm, vfloat32m4_t vs2,
+vfloat8e4m3m1_t test_vfncvt_f_f_q_f8e4m3m1_m(vbool8_t vm, vfloat32m4_t vs2,
size_t vl) {
return __riscv_vfncvt_f_f_q_f8e4m3m1_m(vm, vs2, vl);
}
@@ -190,7 +190,7 @@ vuint8m1_t test_vfncvt_f_f_q_f8e4m3m1_m(vbool8_t vm, vfloat32m4_t vs2,
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vfncvt_sat_f_f_q_f8e4m3m1_m(vbool8_t vm, vfloat32m4_t vs2,
+vfloat8e4m3m1_t ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/191626
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