[clang] [llvm] [AMDGPU] First installment of IGLP_OPT 4 (MFMAValuSpacingOpt) implementation (PR #190916)

[Matt Arsenault via cfe-commits]

================
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; Full codegen on gfx950.  Two MFMAs fed by loaded floats; three independent
+; i32 muls stored to a second buffer.  sched.barrier(0) isolates the MUL+MFMA
+; region so that address-computation VALUs don't inflate the VALU gap in
+; MFMAValuSpacingOpt.
+;
+; With iglp_opt(4) the expected MFMA/VALU interleaving (ValuGap=1) is:
+;   MFMA, MUL, MFMA, MUL, MUL
+;
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -o - %s | FileCheck %s
----------------
arsenm wrote:

```suggestion
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s
```

https://github.com/llvm/llvm-project/pull/190916