[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #188609)

[via cfe-commits]

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@@ -182,6 +182,11 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
+
+  unsigned getCSRFirstUseCost() const override {
+    // push + pop.
+    return 2;
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weiguozhi wrote:

Good  catch, skip this optimization for PPX now.

https://github.com/llvm/llvm-project/pull/188609