[clang] [llvm] [SPIR-V] Change DL for logical SPIR-V (PR #190807)
Nathan Gauër via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 8 01:49:12 PDT 2026
https://github.com/Keenuts updated https://github.com/llvm/llvm-project/pull/190807
>From a9bdc0cdae3bd2491598ad9ac4a9bc2a45f52889 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?= <brioche at google.com>
Date: Tue, 7 Apr 2026 14:36:40 +0200
Subject: [PATCH 1/2] [SPIR-V] Change DL for logical SPIR-V
This PR originates from mail at justinbogner.com draft PR.
It modifies the triple for logical SPIR-V to use the new vector
sizing feature.
This means updating the tests, and fix one codegen issue:
on the old triple, we knew a float3 allocation size was the
same as a float4 allocation. This is now invalid, thus
a store <4 x float> into a <3 x float> allocation is UB.
---
clang/lib/Basic/Targets/SPIR.h | 1 +
clang/lib/CodeGen/Targets/SPIR.cpp | 15 ++++++++++
.../CodeGenHLSL/builtins/splitdouble.hlsl | 6 ++--
.../CodeGenHLSL/semantics/SV_Position.ps.hlsl | 4 +--
.../CodeGenHLSL/semantics/SV_Position.vs.hlsl | 4 +--
.../CodeGenHLSL/semantics/SV_Target.ps.hlsl | 2 +-
.../semantics/semantic.arbitrary.hlsl | 2 +-
.../CodeGenHLSL/semantics/semantic.array.hlsl | 4 +--
.../semantics/semantic.array.output.hlsl | 6 ++--
...antic.explicit-location-output-struct.hlsl | 4 +--
.../semantics/semantic.explicit-location.hlsl | 2 +-
.../semantic.explicit-mix-builtin.hlsl | 10 +++----
.../semantics/semantic.explicit-mix.lib.hlsl | 8 ++---
.../vk.pushconstant.anon-struct.hlsl | 2 +-
clang/test/CodeGenHLSL/vk-input-builtin.hlsl | 2 +-
clang/test/CodeGenHLSL/vk-output-builtin.hlsl | 4 +--
clang/test/CodeGenSPIRV/Builtins/smoothstep.c | 1 +
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 9 +++---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 10 ++++---
llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 2 +-
llvm/lib/TargetParser/TargetDataLayout.cpp | 3 +-
.../CodeGen/SPIRV/hlsl-resources/Packed.ll | 12 ++------
.../hlsl-resources/cbuffer-peeled-array.ll | 6 ++--
.../load-vector-from-array-of-vectors.ll | 10 +++----
.../CodeGen/SPIRV/spirv-explicit-layout.ll | 8 ++---
.../SPIRV/vk-pushconstant-layout-natural.ll | 29 +++++++++++++++++++
.../CodeGen/SPIRV/vk-pushconstant-layout.ll | 5 ++--
.../Target/SPIRV/SPIRVGlobalRegistryTests.cpp | 2 +-
28 files changed, 104 insertions(+), 69 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index 5570a9c55a508..37fe4a970dfef 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -351,6 +351,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRVTargetInfo : public BaseSPIRVTargetInfo {
// SPIR-V IDs are represented with a single 32-bit word.
SizeType = TargetInfo::UnsignedInt;
+ VectorsAreElementAligned = true;
resetDataLayout();
}
diff --git a/clang/lib/CodeGen/Targets/SPIR.cpp b/clang/lib/CodeGen/Targets/SPIR.cpp
index 4d902fe2d6e3e..d5122f8d65a3e 100644
--- a/clang/lib/CodeGen/Targets/SPIR.cpp
+++ b/clang/lib/CodeGen/Targets/SPIR.cpp
@@ -39,6 +39,10 @@ class SPIRVABIInfo : public CommonSPIRABIInfo {
RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
AggValueSlot Slot) const override;
+ llvm::FixedVectorType *
+ getOptimalVectorMemoryType(llvm::FixedVectorType *Ty,
+ const LangOptions &LangOpt) const override;
+
private:
ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
};
@@ -400,6 +404,17 @@ void AMDGCNSPIRVABIInfo::computeInfo(CGFunctionInfo &FI) const {
}
}
+llvm::FixedVectorType *
+SPIRVABIInfo::getOptimalVectorMemoryType(llvm::FixedVectorType *Ty,
+ const LangOptions &LangOpt) const {
+ // For Logical SPIR-V, we don't know the underlying hardware or layout.
+ // This means we don't know which vector size is better, and also cannot
+ // assume a smaller vector size is stored in a larger vector size.
+ if (getTarget().getTriple().isSPIRVLogical())
+ return Ty;
+ return DefaultABIInfo::getOptimalVectorMemoryType(Ty, LangOpt);
+}
+
llvm::FixedVectorType *AMDGCNSPIRVABIInfo::getOptimalVectorMemoryType(
llvm::FixedVectorType *Ty, const LangOptions &LangOpt) const {
// AMDGPU has legal instructions for 96-bit so 3x32 can be supported.
diff --git a/clang/test/CodeGenHLSL/builtins/splitdouble.hlsl b/clang/test/CodeGenHLSL/builtins/splitdouble.hlsl
index 53f4f6aa2cb5f..afacf59ce144e 100644
--- a/clang/test/CodeGenHLSL/builtins/splitdouble.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/splitdouble.hlsl
@@ -46,7 +46,7 @@ uint1 test_double1(double1 D) {
//
// SPIRV: define hidden spir_func {{.*}} <2 x i32> {{.*}}test_vector2{{.*}}(<2 x double> {{.*}} [[VALD:%.*]])
// SPIRV-NOT: @llvm.dx.splitdouble.i32
-// SPIRV: [[LOAD:%.*]] = load <2 x double>, ptr [[VALD]].addr, align 16
+// SPIRV: [[LOAD:%.*]] = load <2 x double>, ptr [[VALD]].addr, align 8
// SPIRV-NEXT: [[CAST1:%.*]] = bitcast <2 x double> [[LOAD]] to <4 x i32>
// SPIRV-NEXT: [[SHUF1:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>
// SPIRV-NEXT: [[SHUF2:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>
@@ -63,7 +63,7 @@ uint2 test_vector2(double2 D) {
//
// SPIRV: define hidden spir_func {{.*}} <3 x i32> {{.*}}test_vector3{{.*}}(<3 x double> {{.*}} [[VALD:%.*]])
// SPIRV-NOT: @llvm.dx.splitdouble.i32
-// SPIRV: [[LOAD:%.*]] = load <3 x double>, ptr [[VALD]].addr, align 32
+// SPIRV: [[LOAD:%.*]] = load <3 x double>, ptr [[VALD]].addr, align 8
// SPIRV-NEXT: [[CAST1:%.*]] = bitcast <3 x double> [[LOAD]] to <6 x i32>
// SPIRV-NEXT: [[SHUF1:%.*]] = shufflevector <6 x i32> [[CAST1]], <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4>
// SPIRV-NEXT: [[SHUF2:%.*]] = shufflevector <6 x i32> [[CAST1]], <6 x i32> poison, <3 x i32> <i32 1, i32 3, i32 5>
@@ -80,7 +80,7 @@ uint3 test_vector3(double3 D) {
//
// SPIRV: define hidden spir_func {{.*}} <4 x i32> {{.*}}test_vector4{{.*}}(<4 x double> {{.*}} [[VALD:%.*]])
// SPIRV-NOT: @llvm.dx.splitdouble.i32
-// SPIRV: [[LOAD:%.*]] = load <4 x double>, ptr [[VALD]].addr, align 32
+// SPIRV: [[LOAD:%.*]] = load <4 x double>, ptr [[VALD]].addr, align 8
// SPIRV-NEXT: [[CAST1:%.*]] = bitcast <4 x double> [[LOAD]] to <8 x i32>
// SPIRV-NEXT: [[SHUF1:%.*]] = shufflevector <8 x i32> [[CAST1]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
// SPIRV-NEXT: [[SHUF2:%.*]] = shufflevector <8 x i32> [[CAST1]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
diff --git a/clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl b/clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
index b7d2283ea7766..b118ee395f7de 100644
--- a/clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
@@ -5,9 +5,9 @@
// CHECK: define void @main() {{.*}} {
float4 main(float4 p : SV_Position) : A {
- // CHECK-SPIRV: %[[#P:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 16
+ // CHECK-SPIRV: %[[#P:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 4
// CHECK-SPIRV: %[[#R:]] = call spir_func <4 x float> @_Z4mainDv4_f(<4 x float> %[[#P]])
- // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @A0, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @A0, align 4
// CHECK-DXIL: %SV_Position0 = call <4 x float> @llvm.dx.load.input.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison)
// CHECK-DXIL: %[[#TMP:]] = call <4 x float> @_Z4mainDv4_f(<4 x float> %SV_Position0)
diff --git a/clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl b/clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
index 0156c0bb816c1..caab744c1fa98 100644
--- a/clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/SV_Position.vs.hlsl
@@ -6,9 +6,9 @@
// CHECK: define void @main() {{.*}} {
float4 main(float4 p : SV_Position) : SV_Position {
- // CHECK-SPIRV: %[[#P:]] = load <4 x float>, ptr addrspace(7) @SV_Position0, align 16
+ // CHECK-SPIRV: %[[#P:]] = load <4 x float>, ptr addrspace(7) @SV_Position0, align 4
// CHECK-SPIRV: %[[#R:]] = call spir_func <4 x float> @_Z4mainDv4_f(<4 x float> %[[#P]])
- // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Position, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Position, align 4
// CHECK-DXIL: %SV_Position0 = call <4 x float> @llvm.dx.load.input.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison)
// CHECK-DXIL: %[[#TMP:]] = call <4 x float> @_Z4mainDv4_f(<4 x float> %SV_Position0)
diff --git a/clang/test/CodeGenHLSL/semantics/SV_Target.ps.hlsl b/clang/test/CodeGenHLSL/semantics/SV_Target.ps.hlsl
index 4dc622a1eb6bb..1ab4df4f61bd7 100644
--- a/clang/test/CodeGenHLSL/semantics/SV_Target.ps.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/SV_Target.ps.hlsl
@@ -6,7 +6,7 @@
// CHECK: define void @main() {{.*}} {
float4 main(float4 p : SV_Position) : SV_Target {
// CHECK-SPIRV: %[[#R:]] = call spir_func <4 x float> @_Z4mainDv4_f(<4 x float> %[[#]])
- // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 4
// CHECK-DXIL: %[[#TMP:]] = call <4 x float> @_Z4mainDv4_f(<4 x float> %SV_Position0)
// CHECK-DXIL: call void @llvm.dx.store.output.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison, <4 x float> %[[#TMP]])
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.arbitrary.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.arbitrary.hlsl
index 96d5b995fa74a..1ea2827660307 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.arbitrary.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.arbitrary.hlsl
@@ -21,7 +21,7 @@ void main(float a : AAA, int b : B, float2 c : CC) {
// CHECK-SPIRV: %[[#AAA0:]] = load float, ptr addrspace(7) @AAA0, align 4
// CHECK-SPIRV: %[[#B0:]] = load i32, ptr addrspace(7) @B0, align 4
-// CHECK-SPIRV: %[[#CC0:]] = load <2 x float>, ptr addrspace(7) @CC0, align 8
+// CHECK-SPIRV: %[[#CC0:]] = load <2 x float>, ptr addrspace(7) @CC0, align 4
// CHECK-SPIRV: call spir_func void @_Z4mainfiDv2_f(float %[[#AAA0]], i32 %[[#B0]], <2 x float> %[[#CC0]]) [ "convergencectrl"(token %0) ]
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.array.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.array.hlsl
index 445a1f5a33f12..c62c4d4a517f2 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.array.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.array.hlsl
@@ -17,9 +17,9 @@ struct S0 {
// CHECK-DXIL: %A2 = call <4 x float> @llvm.dx.load.input.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison)
// CHECK-DXIL: %[[#TMP1:]] = insertvalue %struct.S0 %[[#TMP0]], <4 x float> %A2, 1
-// CHECK-SPIRV: %[[#A0:]] = load [2 x <4 x float>], ptr addrspace(7) @A0, align 16
+// CHECK-SPIRV: %[[#A0:]] = load [2 x <4 x float>], ptr addrspace(7) @A0, align 4
// CHECK-SPIRV: %[[#TMP0:]] = insertvalue %struct.S0 poison, [2 x <4 x float>] %[[#A0]], 0
-// CHECK-SPIRV: %[[#A01:]] = load <4 x float>, ptr addrspace(7) @A2, align 16
+// CHECK-SPIRV: %[[#A01:]] = load <4 x float>, ptr addrspace(7) @A2, align 4
// CHECK-SPIRV: %[[#TMP1:]] = insertvalue %struct.S0 %[[#TMP0]], <4 x float> %[[#A01]], 1
// CHECK: %[[#ARG:]] = alloca %struct.S0
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
index 7662b9ab881d9..18942699aaa2c 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
@@ -11,17 +11,17 @@ struct S0 {
[shader("pixel")]
S0 main1(float4 input : A) : B {
// CHECK: %[[#ARG:]] = alloca %struct.S0
-// CHECK-SPIRV: %[[#INPUT:]] = load <4 x float>, ptr addrspace(7) @A0, align 16
+// CHECK-SPIRV: %[[#INPUT:]] = load <4 x float>, ptr addrspace(7) @A0, align 4
// CHECK-DXIL: %A0 = call <4 x float> @llvm.dx.load.input.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison)
// CHECK-DXIL: call void @{{.*}}main1{{.*}}(ptr %[[#ARG]], <4 x float> %A0)
// CHECK-SPIRV: call spir_func void @{{.*}}main1{{.*}}(ptr %[[#ARG]], <4 x float> %[[#INPUT]])
// CHECK: %[[#ST:]] = load %struct.S0, ptr %[[#ARG]]
// CHECK: %[[#TMP:]] = extractvalue %struct.S0 %[[#ST]], 0
- // CHECK-SPIRV: store [2 x <4 x float>] %[[#TMP]], ptr addrspace(8) @B0, align 16
+ // CHECK-SPIRV: store [2 x <4 x float>] %[[#TMP]], ptr addrspace(8) @B0, align 4
// CHECK-DXIL: call void @llvm.dx.store.output.a2v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison, [2 x <4 x float>] %[[#TMP]])
// CHECK: %[[#TMP:]] = extractvalue %struct.S0 %[[#ST]], 1
- // CHECK-SPIRV: store <4 x float> %[[#TMP]], ptr addrspace(8) @B2, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#TMP]], ptr addrspace(8) @B2, align 4
// CHECK-DXIL: call void @llvm.dx.store.output.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison, <4 x float> %[[#TMP]])
S0 output;
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.explicit-location-output-struct.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.explicit-location-output-struct.hlsl
index 124badf756610..8bd8998cdceb5 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.explicit-location-output-struct.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.explicit-location-output-struct.hlsl
@@ -12,7 +12,7 @@ struct Output {
Output main(float4 p : SV_Position) {
// CHECK: %[[#OUT:]] = alloca %struct.Output
- // CHECK-SPIRV: %[[#IN:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 16
+ // CHECK-SPIRV: %[[#IN:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 4
// CHECK-SPIRV: call spir_func void @_Z4mainDv4_f(ptr %[[#OUT]], <4 x float> %[[#IN]])
// CHECK-DXIL: call void @_Z4mainDv4_f(ptr %[[#OUT]], <4 x float> %SV_Position0)
@@ -20,7 +20,7 @@ Output main(float4 p : SV_Position) {
// CHECK: %[[#TMP:]] = load %struct.Output, ptr %[[#OUT]]
// CHECK: %[[#FIELD:]] = extractvalue %struct.Output %[[#TMP]], 0
- // CHECK-SPIRV: store <4 x float> %[[#FIELD]], ptr addrspace(8) @SV_Target0, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#FIELD]], ptr addrspace(8) @SV_Target0, align 4
// CHECK-DXIL: call void @llvm.dx.store.output.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison, <4 x float> %[[#FIELD]])
Output o;
o.field = p;
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.explicit-location.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.explicit-location.hlsl
index 41e28bf1259d6..625d5dcb02ec4 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.explicit-location.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.explicit-location.hlsl
@@ -6,7 +6,7 @@
// CHECK: define void @main() {{.*}} {
[[vk::location(2)]] float4 main(float4 p : SV_Position) : SV_Target {
// CHECK-SPIRV: %[[#R:]] = call spir_func <4 x float> @_Z4mainDv4_f(<4 x float> %[[#]])
- // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 16
+ // CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 4
// CHECK-DXIL: %[[#TMP:]] = call <4 x float> @_Z4mainDv4_f(<4 x float> %SV_Position0)
// CHECK-DXIL: call void @llvm.dx.store.output.v4f32(i32 4, i32 0, i32 0, i8 0, i32 poison, <4 x float> %[[#TMP]])
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.hlsl
index bc2ecd926dd51..024310ad34d47 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.hlsl
@@ -22,14 +22,14 @@ struct S1 {
float4 main(S1 p) : SV_Target {
return p.position + p.color0;
}
-// CHECK-SPIRV: %[[#SV_POS:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 16
+// CHECK-SPIRV: %[[#SV_POS:]] = load <4 x float>, ptr addrspace(7) @SV_Position, align 4
// CHECK: %[[#TMP1:]] = insertvalue %struct.S1 poison, <4 x float> %[[#SV_POS]], 0
-// CHECK-SPIRV: %[[#A0:]] = load <4 x float>, ptr addrspace(7) @COLOR0, align 16
+// CHECK-SPIRV: %[[#A0:]] = load <4 x float>, ptr addrspace(7) @COLOR0, align 4
// CHECK: %[[#TMP2:]] = insertvalue %struct.S1 %[[#TMP1]], <4 x float> %[[#A0]], 1
-// CHECK: %[[#P:]] = alloca %struct.S1, align 16
-// CHECK: store %struct.S1 %[[#TMP2]], ptr %[[#P]], align 16
+// CHECK: %[[#P:]] = alloca %struct.S1, align 8
+// CHECK: store %struct.S1 %[[#TMP2]], ptr %[[#P]], align 4
// CHECK-SPIRV: %[[#R:]] = call spir_func <4 x float> @_Z4main2S1(ptr %[[#P]])
-// CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 16
+// CHECK-SPIRV: store <4 x float> %[[#R]], ptr addrspace(8) @SV_Target0, align 4
// CHECK-SPIRV: ![[#MD_0]] = !{![[#MD_1:]]}
// CHECK-SPIRV: ![[#MD_1]] = !{i32 11, i32 15}
diff --git a/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix.lib.hlsl b/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix.lib.hlsl
index 456c9bf9aee05..793241a329548 100644
--- a/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix.lib.hlsl
+++ b/clang/test/CodeGenHLSL/semantics/semantic.explicit-mix.lib.hlsl
@@ -27,12 +27,12 @@ float4 not_an_entry([[vk::location(0)]] float4 a : A, float4 b : B) : C {
// CHECK: define void @vs_main()
-// CHECK: %[[#]] = load <4 x float>, ptr addrspace(7) @SV_Position0, align 16
-// CHECK: store <4 x float> %[[#]], ptr addrspace(8) @A0, align 16
+// CHECK: %[[#]] = load <4 x float>, ptr addrspace(7) @SV_Position0, align 4
+// CHECK: store <4 x float> %[[#]], ptr addrspace(8) @A0, align 4
// CHECK: define void @ps_main()
-// CHECK: %[[#]] = load <4 x float>, ptr addrspace(7) @A0.1, align 16
-// CHECK: store <4 x float> %[[#]], ptr addrspace(8) @SV_Target0, align 16
+// CHECK: %[[#]] = load <4 x float>, ptr addrspace(7) @A0.1, align 4
+// CHECK: store <4 x float> %[[#]], ptr addrspace(8) @SV_Target0, align 4
// CHECK: ![[#MD_0]] = !{![[#MD_1:]]}
// CHECK: ![[#MD_1]] = !{i32 30, i32 0}
diff --git a/clang/test/CodeGenHLSL/vk-features/vk.pushconstant.anon-struct.hlsl b/clang/test/CodeGenHLSL/vk-features/vk.pushconstant.anon-struct.hlsl
index 2b2e9d09c7ab0..c5b040adb0193 100644
--- a/clang/test/CodeGenHLSL/vk-features/vk.pushconstant.anon-struct.hlsl
+++ b/clang/test/CodeGenHLSL/vk-features/vk.pushconstant.anon-struct.hlsl
@@ -8,7 +8,7 @@ struct {
}
PushConstants;
-// CHECK: %struct.anon = type <{ i32, float, <3 x float> }>
+// CHECK: %struct.anon = type { i32, float, <3 x float> }
// CHECK: @PushConstants = external hidden addrspace(13) externally_initialized global %struct.anon, align 1
[numthreads(1, 1, 1)]
diff --git a/clang/test/CodeGenHLSL/vk-input-builtin.hlsl b/clang/test/CodeGenHLSL/vk-input-builtin.hlsl
index 157a1818c82ff..cbf79738a953f 100644
--- a/clang/test/CodeGenHLSL/vk-input-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/vk-input-builtin.hlsl
@@ -3,7 +3,7 @@
[[vk::ext_builtin_input(/* WorkgroupId */ 26)]]
static const uint3 groupid;
-// CHECK: @_ZL7groupid = external hidden local_unnamed_addr addrspace(7) externally_initialized constant <3 x i32>, align 16, !spirv.Decorations [[META0:![0-9]+]]
+// CHECK: @_ZL7groupid = external hidden local_unnamed_addr addrspace(7) externally_initialized constant <3 x i32>, align 4, !spirv.Decorations [[META0:![0-9]+]]
RWStructuredBuffer<int> output : register(u1, space0);
diff --git a/clang/test/CodeGenHLSL/vk-output-builtin.hlsl b/clang/test/CodeGenHLSL/vk-output-builtin.hlsl
index df521113476eb..3ca2b6c149af8 100644
--- a/clang/test/CodeGenHLSL/vk-output-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/vk-output-builtin.hlsl
@@ -3,13 +3,13 @@
[[vk::ext_builtin_output(/* Position */ 0)]]
static float4 position;
-// CHECK: @position = external hidden local_unnamed_addr addrspace(8) global <4 x float>, align 16, !spirv.Decorations [[META0:![0-9]+]]
+// CHECK: @position = external hidden local_unnamed_addr addrspace(8) global <4 x float>, align 4, !spirv.Decorations [[META0:![0-9]+]]
RWStructuredBuffer<float4> input : register(u1, space0);
void main() {
position = input[0];
- // CHECK: store <4 x float> %[[#]], ptr addrspace(8) @position, align 16
+ // CHECK: store <4 x float> %[[#]], ptr addrspace(8) @position, align 4
}
// CHECK: [[META0]] = !{[[META1:![0-9]+]]}
// CHECK: [[META1]] = !{i32 11, i32 0}
diff --git a/clang/test/CodeGenSPIRV/Builtins/smoothstep.c b/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
index 714db4d9f728c..bf24876f3b6ae 100644
--- a/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
+++ b/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
@@ -1,5 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 -O1 -triple spirv-pc-vulkan-compute %s -emit-llvm -o - -mllvm -print-before-all
// RUN: %clang_cc1 -O1 -triple spirv-pc-vulkan-compute %s -emit-llvm -o - | FileCheck %s
typedef float float2 __attribute__((ext_vector_type(2)));
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 50f672768f141..09ee9a466bfcd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -88,8 +88,8 @@ storageClassRequiresExplictLayout(SPIRV::StorageClass::StorageClass SC) {
llvm_unreachable("Unknown SPIRV::StorageClass enum");
}
-SPIRVGlobalRegistry::SPIRVGlobalRegistry(unsigned PointerSize)
- : PointerSize(PointerSize), Bound(0), CurMF(nullptr) {}
+SPIRVGlobalRegistry::SPIRVGlobalRegistry(DataLayout DL)
+ : DL(DL), Bound(0), CurMF(nullptr) {}
SPIRVTypeInst
SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, Register VReg,
@@ -763,7 +763,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
if (Res.isValid())
return Res;
- LLT LLTy = LLT::pointer(AddressSpace, PointerSize);
+ LLT LLTy = LLT::pointer(AddressSpace, getPointerSize());
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::pIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
@@ -2280,7 +2280,6 @@ void SPIRVGlobalRegistry::updateAssignType(CallInst *AssignCI, Value *Arg,
void SPIRVGlobalRegistry::addStructOffsetDecorations(
Register Reg, StructType *Ty, MachineIRBuilder &MIRBuilder) {
- DataLayout DL;
ArrayRef<TypeSize> Offsets = DL.getStructLayout(Ty)->getMemberOffsets();
for (uint32_t I = 0; I < Ty->getNumElements(); ++I) {
buildOpMemberDecorate(Reg, MIRBuilder, SPIRV::Decoration::Offset, I,
@@ -2290,7 +2289,7 @@ void SPIRVGlobalRegistry::addStructOffsetDecorations(
void SPIRVGlobalRegistry::addArrayStrideDecorations(
Register Reg, Type *ElementType, MachineIRBuilder &MIRBuilder) {
- uint32_t SizeInBytes = DataLayout().getTypeSizeInBits(ElementType) / 8;
+ uint32_t SizeInBytes = DL.getTypeSizeInBits(ElementType) / 8;
buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::ArrayStride,
{SizeInBytes});
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 7adab18e150b9..f05bdc2cc9861 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -67,8 +67,8 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
// if a function returns a pointer, this is to map it into TypedPointerType
DenseMap<const Function *, TypedPointerType *> FunResPointerTypes;
- // Number of bits pointers and size_t integers require.
- const unsigned PointerSize;
+ // Current target's datalayout.
+ DataLayout DL;
// Holds the maximum ID we have in the module.
unsigned Bound;
@@ -112,7 +112,7 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
std::function<MachineInstr *(MachineIRBuilder &)> Op);
public:
- SPIRVGlobalRegistry(unsigned PointerSize);
+ SPIRVGlobalRegistry(DataLayout DL);
MachineFunction *CurMF;
@@ -418,7 +418,9 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
getPointerStorageClass(SPIRVTypeInst Type) const;
// Return the number of bits SPIR-V pointers and size_t variables require.
- unsigned getPointerSize() const { return PointerSize; }
+ unsigned getPointerSize() const {
+ return DL.getPointerSizeInBits(/* AS = */ 0);
+ }
// Returns true if two types are defined and are compatible in a sense of
// OpBitcast instruction
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
index 4aca400e827d7..e4c98984bf0af 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
@@ -109,7 +109,7 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU,
initAvailableExtensions(Extensions);
initAvailableExtInstSets();
- GR = std::make_unique<SPIRVGlobalRegistry>(PointerSize);
+ GR = std::make_unique<SPIRVGlobalRegistry>(TM.createDataLayout());
CallLoweringInfo = std::make_unique<SPIRVCallLowering>(TLInfo, GR.get());
InlineAsmInfo = std::make_unique<SPIRVInlineAsmLowering>(TLInfo);
Legalizer = std::make_unique<SPIRVLegalizerInfo>(*this);
diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp
index 91c41103a564c..231d62f6c0f93 100644
--- a/llvm/lib/TargetParser/TargetDataLayout.cpp
+++ b/llvm/lib/TargetParser/TargetDataLayout.cpp
@@ -473,8 +473,7 @@ static std::string computeSPIRVDataLayout(const Triple &TT) {
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
"v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
if (Arch == Triple::spirv)
- return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
- "v512:512-v1024:1024-n8:16:32:64-G10";
+ return "e-ve-i64:64-n8:16:32:64-G10";
if (TT.getVendor() == Triple::VendorType::AMD &&
TT.getOS() == Triple::OSType::AMDHSA)
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/Packed.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/Packed.ll
index 15a1a3291fcb1..9649f5a02933d 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-resources/Packed.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/Packed.ll
@@ -1,22 +1,16 @@
; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv1.6-vulkan1.3-library %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-vulkan1.3-library %s -o - -filetype=obj | spirv-val %}
-target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
-
-
@.str.unpacked = private unnamed_addr constant [12 x i8] c"UnpackedRes\00", align 1
@.str.packed = private unnamed_addr constant [10 x i8] c"PackedRes\00", align 1
; CHECK-DAG: OpName [[unpacked:%[0-9]+]] "unpacked"
-; CHECK-DAG: OpName [[packed:%[0-9]+]] "packed"
+; CHECK-DAG: OpName [[unpacked]] "packed"
+; Both packed and unpacked version have the same layout in SPIR-V.
; CHECK-NOT: OpDecorate {{.*}} CPacked
; CHECK-DAG: OpMemberDecorate [[unpacked]] 0 Offset 0
-; CHECK-DAG: OpMemberDecorate [[unpacked]] 1 Offset 16
-
-; CHECK-NOT: OpDecorate {{.*}} CPacked
-; CHECK-DAG: OpMemberDecorate [[packed]] 0 Offset 0
-; CHECK-DAG: OpMemberDecorate [[packed]] 1 Offset 4
+; CHECK-DAG: OpMemberDecorate [[unpacked]] 1 Offset 4
; CHECK-NOT: OpDecorate {{.*}} CPacked
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
index 65447b4f3d26d..49b539c506714 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/cbuffer-peeled-array.ll
@@ -17,11 +17,9 @@
; CHECK-DAG: %[[MYCBUFFER:[0-9]+]] = OpVariable %[[PTR_WRAPPER]] Uniform
-; TODO(168401): This array stride and offset of element 1 are incorrect. This
-; is an issue with how 3 element vectors are handled.
-; CHECK-DAG: OpDecorate %[[ARRAY]] ArrayStride 20
+; CHECK-DAG: OpDecorate %[[ARRAY]] ArrayStride 16
; CHECK-DAG: OpMemberDecorate %[[STRUCT_PAD]] 0 Offset 0
-; CHECK-DAG: OpMemberDecorate %[[STRUCT_PAD]] 1 Offset 16
+; CHECK-DAG: OpMemberDecorate %[[STRUCT_PAD]] 1 Offset 12
; CHECK-DAG: OpMemberDecorate %[[WRAPPER]] 0 Offset 0
; CHECK-DAG: OpDecorate %[[WRAPPER]] Block
%__cblayout_MyCBuffer = type <{ <{ [2 x <{ <3 x float>, target("spirv.Padding", 4) }>], <3 x float> }> }>
diff --git a/llvm/test/CodeGen/SPIRV/pointers/load-vector-from-array-of-vectors.ll b/llvm/test/CodeGen/SPIRV/pointers/load-vector-from-array-of-vectors.ll
index 5a9a1cb4a4fb7..8c28e6a3212c3 100644
--- a/llvm/test/CodeGen/SPIRV/pointers/load-vector-from-array-of-vectors.ll
+++ b/llvm/test/CodeGen/SPIRV/pointers/load-vector-from-array-of-vectors.ll
@@ -10,27 +10,27 @@
; // M1[0][0]
; IRCHECK: [[M1ROWZero:%[0-9]+]] = call ptr addrspace(10) (i1, ptr addrspace(10), ...) @llvm.spv.gep.p10.p10(i1 false, ptr addrspace(10) @M1, i32 0, i32 0)
-; IRCHECK: [[M1ROWZeroVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWZero]], align 8
+; IRCHECK: [[M1ROWZeroVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWZero]], align 4
; IRCHECK: [[M1Elem_00:%[0-9]+]] = call float @llvm.spv.extractelt.f32.v2f32.i32(<2 x float> [[M1ROWZeroVec]], i32 0)
;// M1[0][1]
; IRCHECK: [[M1ROWZero_2:%[0-9]+]] = call ptr addrspace(10) (i1, ptr addrspace(10), ...) @llvm.spv.gep.p10.p10(i1 false, ptr addrspace(10) @M1, i32 0, i32 0)
-; IRCHECK: [[M1ROWZeroVec_2:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWZero_2]], align 8
+; IRCHECK: [[M1ROWZeroVec_2:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWZero_2]], align 4
; IRCHECK: [[M1Elem_01:%[0-9]+]] = call float @llvm.spv.extractelt.f32.v2f32.i32(<2 x float> [[M1ROWZeroVec_2]], i32 1)
; // M1[1][0]
; IRCHECK: [[M1ROWOne:%[0-9]+]] = call ptr addrspace(10) (i1, ptr addrspace(10), ...) @llvm.spv.gep.p10.p10(i1 false, ptr addrspace(10) @M1, i32 0, i32 1)
-; IRCHECK: [[M1ROWOneVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWOne]], align 8
+; IRCHECK: [[M1ROWOneVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWOne]], align 4
; IRCHECK: [[M1Elem_10:%[0-9]+]] = call float @llvm.spv.extractelt.f32.v2f32.i32(<2 x float> [[M1ROWOneVec]], i32 0)
; // M1[1][1]
; IRCHECK: [[M1ROWOne_2:%[0-9]+]] = call ptr addrspace(10) (i1, ptr addrspace(10), ...) @llvm.spv.gep.p10.p10(i1 false, ptr addrspace(10) @M1, i32 0, i32 1)
-; IRCHECK: [[M1ROWOneVec_2:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWOne_2]], align 8
+; IRCHECK: [[M1ROWOneVec_2:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWOne_2]], align 4
; IRCHECK: [[M1Elem_11:%[0-9]+]] = call float @llvm.spv.extractelt.f32.v2f32.i32(<2 x float> [[M1ROWOneVec_2]], i32 1)
; // M1[2][0]
; IRCHECK: [[M1ROWTwo:%[0-9]+]] = call ptr addrspace(10) (i1, ptr addrspace(10), ...) @llvm.spv.gep.p10.p10(i1 false, ptr addrspace(10) @M1, i32 0, i32 2)
-; IRCHECK: [[M1ROWTwoVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWTwo]], align 8
+; IRCHECK: [[M1ROWTwoVec:%[0-9]+]] = load <2 x float>, ptr addrspace(10) [[M1ROWTwo]], align 4
; IRCHECK: [[M1Elem_20:%[0-9]+]] = call float @llvm.spv.extractelt.f32.v2f32.i32(<2 x float> [[M1ROWTwoVec]], i32 0)
@M1 = internal addrspace(10) global [4 x <2 x float>] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/SPIRV/spirv-explicit-layout.ll b/llvm/test/CodeGen/SPIRV/spirv-explicit-layout.ll
index 9bdf75acfa65e..9997ae53c0947 100644
--- a/llvm/test/CodeGen/SPIRV/spirv-explicit-layout.ll
+++ b/llvm/test/CodeGen/SPIRV/spirv-explicit-layout.ll
@@ -1,8 +1,6 @@
; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv1.6-vulkan1.3-library %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-vulkan1.3-library %s -o - -filetype=obj | spirv-val %}
-target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64-G1"
-
@.str.scalarblock = private unnamed_addr constant [12 x i8] c"ScalarBlock\00", align 1
@.str.buffervar = private unnamed_addr constant [10 x i8] c"BufferVar\00", align 1
@.str.arraybuffervar = private unnamed_addr constant [15 x i8] c"ArrayBufferVar\00", align 1
@@ -16,10 +14,10 @@ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:
; CHECK-DAG: OpDecorate [[ScalarBlock]] Block
; CHECK-DAG: OpMemberDecorate [[ScalarBlock]] 0 NonWritable
; CHECK-DAG: OpMemberDecorate [[T_explicit:%[0-9]+]] 0 Offset 0
-; CHECK-DAG: OpMemberDecorate [[T_explicit]] 1 Offset 16
-; CHECK-DAG: OpDecorate [[T_array_explicit:%[0-9]+]] ArrayStride 32
+; CHECK-DAG: OpMemberDecorate [[T_explicit]] 1 Offset 4
+; CHECK-DAG: OpDecorate [[T_array_explicit:%[0-9]+]] ArrayStride 16
; CHECK-DAG: OpMemberDecorate [[S_explicit:%[0-9]+]] 0 Offset 0
-; CHECK-DAG: OpDecorate [[S_array_explicit:%[0-9]+]] ArrayStride 320
+; CHECK-DAG: OpDecorate [[S_array_explicit:%[0-9]+]] ArrayStride 160
; CHECK-DAG: OpMemberDecorate [[block:%[0-9]+]] 0 Offset 0
; CHECK-DAG: OpDecorate [[block]] Block
; CHECK-DAG: OpMemberDecorate [[block]] 0 NonWritable
diff --git a/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll b/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll
new file mode 100644
index 0000000000000..03ed408651887
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout-natural.ll
@@ -0,0 +1,29 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s
+
+%struct.anon = type { i32, float, <3 x float> }
+
+; CHECK-DAG: %[[#F32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#V3F32:]] = OpTypeVector %[[#F32]] 3
+; CHECK-DAG: %[[#UINT:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#STRUCT:]] = OpTypeStruct %[[#UINT]] %[[#F32]] %[[#V3F32]]
+
+; CHECK-DAG: OpMemberDecorate %[[#STRUCT]] 0 Offset 0
+; CHECK-DAG: OpMemberDecorate %[[#STRUCT]] 1 Offset 4
+; CHECK-DAG: OpMemberDecorate %[[#STRUCT]] 2 Offset 8
+; CHECK-DAG: OpDecorate %[[#STRUCT]] Block
+
+; CHECK-DAG: %[[#PTR_PCS:]] = OpTypePointer PushConstant %[[#STRUCT]]
+
+ at PushConstants = external hidden addrspace(13) externally_initialized global %struct.anon, align 1
+; CHECK: %[[#PCS:]] = OpVariable %[[#PTR_PCS]] PushConstant
+
+define void @main() #1 {
+entry:
+ %0 = call token @llvm.experimental.convergence.entry()
+ ret void
+}
+
+declare token @llvm.experimental.convergence.entry() #2
+
+attributes #1 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" }
+attributes #2 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
diff --git a/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll b/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
index c61375e85c47f..09b2c569b4d0c 100644
--- a/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
+++ b/llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
@@ -3,12 +3,10 @@
; FIXME(168401): fix the offset of last struct S field.
%struct.T = type { [3 x <2 x float>] }
-%struct.S = type <{ float, <3 x float>, %struct.T }>
+%struct.S = type { float, <3 x float>, %struct.T }
; CHECK-NOT: OpCapability Linkage
-; CHECK-DAG: %[[#PTR_PCS:]] = OpTypePointer PushConstant %[[#S_S:]]
-
; CHECK-DAG: %[[#F32:]] = OpTypeFloat 32
; CHECK-DAG: %[[#V3F32:]] = OpTypeVector %[[#F32]] 3
; CHECK-DAG: %[[#V2F32:]] = OpTypeVector %[[#F32]] 2
@@ -26,6 +24,7 @@
; CHECK-DAG: OpDecorate %[[#S_S]] Block
; CHECK-DAG: OpDecorate %[[#ARR]] ArrayStride 8
+; CHECK-DAG: %[[#PTR_PCS:]] = OpTypePointer PushConstant %[[#S_S:]]
@pcs = external hidden addrspace(13) externally_initialized global %struct.S, align 1
; CHECK: %[[#PCS:]] = OpVariable %[[#PTR_PCS]] PushConstant
diff --git a/llvm/unittests/Target/SPIRV/SPIRVGlobalRegistryTests.cpp b/llvm/unittests/Target/SPIRV/SPIRVGlobalRegistryTests.cpp
index 80364def71367..e65a9321b403e 100644
--- a/llvm/unittests/Target/SPIRV/SPIRVGlobalRegistryTests.cpp
+++ b/llvm/unittests/Target/SPIRV/SPIRVGlobalRegistryTests.cpp
@@ -65,7 +65,7 @@ class SPIRVGlobalRegistryTest : public testing::Test {
};
TEST_F(SPIRVGlobalRegistryTest, IsAggregateType) {
- SPIRVGlobalRegistry GR(8);
+ SPIRVGlobalRegistry GR(MF->getDataLayout());
EXPECT_TRUE(GR.isAggregateType(makeTypeInstr(SPIRV::OpTypeStruct)));
EXPECT_TRUE(GR.isAggregateType(makeTypeInstr(SPIRV::OpTypeArray)));
EXPECT_FALSE(GR.isAggregateType(makeTypeInstr(SPIRV::OpTypeFloat)));
>From cd90e660e6f2af27ddb53d4a1e178ff5e312db89 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?= <brioche at google.com>
Date: Wed, 8 Apr 2026 10:47:35 +0200
Subject: [PATCH 2/2] remove bad change
---
clang/test/CodeGenSPIRV/Builtins/smoothstep.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/clang/test/CodeGenSPIRV/Builtins/smoothstep.c b/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
index bf24876f3b6ae..714db4d9f728c 100644
--- a/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
+++ b/clang/test/CodeGenSPIRV/Builtins/smoothstep.c
@@ -1,6 +1,5 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
-// RUN: %clang_cc1 -O1 -triple spirv-pc-vulkan-compute %s -emit-llvm -o - -mllvm -print-before-all
// RUN: %clang_cc1 -O1 -triple spirv-pc-vulkan-compute %s -emit-llvm -o - | FileCheck %s
typedef float float2 __attribute__((ext_vector_type(2)));
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