[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #188609)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> Enable callee saved register optimization implemented in RAGreedy::tryAssignCSRFirstTime() for x86. It can replace save/restore instructions in prologue/epilogue with register spill/reload in cold blocks or register splits.

We don't have hot/cold information without PGO. Should we limit the change when PGO enabled?

> The default value of "regalloc-csr-cost-scale" is changed to 30 according to the result of spec cpu 2006 int with fdo on skylake.

It looks to me the sample is too small and platform is too old. We should be cautious for a global change like this.

https://github.com/llvm/llvm-project/pull/188609