[clang] [CIR][Aarch64] upstream scalar & vector intrinsics (FP16) (PR #190310)

[Andrzej Warzyński via cfe-commits]

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@@ -2122,14 +2122,22 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
   case NEON::BI__builtin_neon_vdups_laneq_f32:
   case NEON::BI__builtin_neon_vgetq_lane_f64:
   case NEON::BI__builtin_neon_vdupd_laneq_f64:
-  case NEON::BI__builtin_neon_vaddh_f16:
-  case NEON::BI__builtin_neon_vsubh_f16:
-  case NEON::BI__builtin_neon_vmulh_f16:
-  case NEON::BI__builtin_neon_vdivh_f16:
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banach-space wrote:

Please preserve the original order - we want to keep this consistent with https://github.com/llvm/llvm-project/blob/8d7823ea8f40cf5df1c623018bf9c0a308fa4a36/clang/lib/CodeGen/TargetBuiltins/ARM.cpp

https://github.com/llvm/llvm-project/pull/190310