[clang] [CIR][AArch64] Lower FP16 vduph lane intrinsics (PR #186955)

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Wed Apr 1 17:01:49 PDT 2026

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neonetizen wrote:

@banach-space Hello! I believe everything should be good to go. I decided to just update this PR because there was an error causing it not to pass the automated checks and I think the rest of the implementations were easy enough (assuming it looks good to you).

https://github.com/llvm/llvm-project/pull/186955

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