[clang] 1264ffc - [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (#110690)

[via cfe-commits]

Author: Kamran Yousafzai
Date: 2026-03-27T16:55:11-07:00
New Revision: 1264ffc4cc17ba8aac19624d478874c2f6bd10d8

URL: https://github.com/llvm/llvm-project/commit/1264ffc4cc17ba8aac19624d478874c2f6bd10d8
DIFF: https://github.com/llvm/llvm-project/commit/1264ffc4cc17ba8aac19624d478874c2f6bd10d8.diff

LOG: [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (#110690)

The code generated for calls with FPCC eligible structs as arguments
doesn't consider the bitfield, which results in a store crossing the
boundary of the memory allocated using alloca, e.g.
For the code:
```
struct __attribute__((packed, aligned(1))) S {
   const float  f0;
   unsigned f1 : 1;
};
unsigned  func(struct S  arg)
{
    return arg.f1;
} 
```
The generated IR is:
```
 define dso_local signext i32 @func(
 float [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
  [[ENTRY:.*:]]
    [[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
    [[TMP2:%.*]] = getelementptr inbounds nuw { float, i32 }, ptr [[ARG]], i32 0, i32 0
    store float [[TMP0]], ptr [[TMP2]], align 1
    [[TMP3:%.*]] = getelementptr inbounds nuw { float, i32 }, ptr [[ARG]], i32 0, i32 1
    store i32 [[TMP1]], ptr [[TMP3]], align 1
    [[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARG]], i32 0, i32 1
    [[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
    [[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
    ret i32 [[BF_CAST]]
```
Where, `store i32 [[TMP1]], ptr [[TMP3]], align 1` can be seen crossing
the boundary of the allocated memory. If, the IR is seen after
optimizations (EarlyCSEPass), the IR left is:
```
 define dso_local noundef signext i32 @func(
 float [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
  [[ENTRY:.*:]]
    ret i32 0
```
The patch trims the second member of the struct after taking into
consideration the bitwidth to decide the appropriate integer type and
the test shows the results of this patch.

Note that the bug is seen only when `f` extension is enabled for FPCC
eligibility.

Co-authored-by: muhammad.kamran4 <muhammad.kamran at esperantotech.com>

Added: 
    clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

Modified: 
    clang/lib/CodeGen/Targets/RISCV.cpp
    clang/test/CodeGen/RISCV/riscv64-abi.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index de51c61a5a0d4..bcf2ee6de4293 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -283,6 +283,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
         // bitwidth is XLen or less.
         if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
           QTy = getContext().getIntTypeForBitwidth(XLen, false);
+        // Trim type to bitwidth if possible
+        else if (getContext().getTypeSize(QTy) > BitWidth) {
+          bool IsSigned =
+              FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+          unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+          QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+        }
         if (BitWidth == 0) {
           ZeroWidthBitFieldCount++;
           continue;

diff  --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 0000000000000..a315b409da613
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr [[ARG]], i32 0, i32 0
+// CHECK-NEXT:    store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr [[ARG]], i32 0, i32 1
+// CHECK-NEXT:    store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:    [[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARG]], i32 0, i32 1
+// CHECK-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:    [[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:    ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+    return arg.f1;
+}

diff  --git a/clang/test/CodeGen/RISCV/riscv64-abi.c b/clang/test/CodeGen/RISCV/riscv64-abi.c
index ce573046b703b..3137792909c2d 100644
--- a/clang/test/CodeGen/RISCV/riscv64-abi.c
+++ b/clang/test/CodeGen/RISCV/riscv64-abi.c
@@ -1747,7 +1747,7 @@ struct float16_int64_s f_ret_float16_int64_s(void) {
 // LP64:  entry:
 //
 // LP64F-LP64D-LABEL: define dso_local void @f_float16_int64bf_s_arg
-// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
+// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //
 void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
@@ -1756,7 +1756,7 @@ void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
 // LP64-SAME: () #[[ATTR0]] {
 // LP64:  entry:
 //
-// LP64F-LP64D-LABEL: define dso_local <{ half, i64 }> @f_ret_float16_int64bf_s
+// LP64F-LP64D-LABEL: define dso_local <{ half, i32 }> @f_ret_float16_int64bf_s
 // LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //