================
@@ -1661,6 +1661,84 @@ def ProcessorFeatures {
];
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
+
+ // Hygon Processors common ISAs
+ list<SubtargetFeature> C864GM4Features = [FeatureADX,
+ FeatureAES,
+ FeatureAVX2,
+ FeatureBMI,
+ FeatureBMI2,
+ FeatureCLFLUSHOPT,
+ FeatureCLZERO,
+ FeatureCMOV,
+ FeatureCRC32,
+ FeatureCX16,
+ FeatureF16C,
+ FeatureFMA,
+ FeatureFSGSBase,
+ FeatureFXSR,
+ FeatureLAHFSAHF64,
+ FeatureLZCNT,
+ FeatureMMX,
+ FeatureMOVBE,
+ FeatureMWAITX,
+ FeatureNOPL,
+ FeaturePCLMUL,
+ FeaturePOPCNT,
+ FeaturePRFCHW,
+ FeatureRDRAND,
+ FeatureRDSEED,
+ FeatureSHA,
+ FeatureSSE4A,
+ FeatureX86_64,
+ FeatureX87,
+ FeatureXSAVE,
+ FeatureXSAVEC,
+ FeatureXSAVEOPT,
+ FeatureXSAVES];
+ list<SubtargetFeature> C864GM4Tuning = [TuningFastLZCNT,
+ TuningFastBEXTR,
+ TuningFast15ByteNOP,
+ TuningFastScalarFSQRT,
+ TuningFastVectorFSQRT,
+ TuningFastScalarShiftMasks,
+ TuningFastVariablePerLaneShuffle,
+ TuningFastMOVBE,
+ TuningFastImm16,
+ TuningSlowDivide64,
+ TuningSlowSHLD,
+ TuningSBBDepBreaking,
+ TuningInsertVZEROUPPER,
+ TuningAllowLight256Bit];
+
+ // C86-4G-M6
----------------
zhangxiaomeng-hygon wrote:
Thanks for the suggestion. In fact, we are planning to add some supports for the M4/M6/M7 microarchitecture features.
https://github.com/llvm/llvm-project/pull/187622