[clang] [Hexagon] Add clang builtins for icinva and isync cache instructions (PR #188413)

[Brian Cain via cfe-commits]

https://github.com/androm3da created https://github.com/llvm/llvm-project/pull/188413

Add __builtin_HEXAGON_Y2_icinva (instruction cache invalidate) and __builtin_HEXAGON_Y2_isync (instruction sync barrier) builtins, along with Q6_icinva_A and Q6_isync convenience macros in hexagon_protos.h.

>From 9aed1f6884ecc7da9fde9ea8d7407a54693bc9d3 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain at oss.qualcomm.com>
Date: Tue, 24 Mar 2026 20:50:09 -0700
Subject: [PATCH] [Hexagon] Add clang builtins for icinva and isync cache
 instructions

Add __builtin_HEXAGON_Y2_icinva (instruction cache invalidate) and
__builtin_HEXAGON_Y2_isync (instruction sync barrier) builtins, along
with Q6_icinva_A and Q6_isync convenience macros in hexagon_protos.h.

These are needed to implement __clear_cache for Hexagon using
intrinsics rather than inline assembly.
---
 clang/include/clang/Basic/BuiltinsHexagon.td |  2 ++
 clang/lib/Headers/hexagon_protos.h           | 18 ++++++++++++++++++
 clang/test/CodeGen/builtins-hexagon.c        |  4 ++++
 3 files changed, 24 insertions(+)

diff --git a/clang/include/clang/Basic/BuiltinsHexagon.td b/clang/include/clang/Basic/BuiltinsHexagon.td
index 00f84cd72a051..8277b178132d7 100644
--- a/clang/include/clang/Basic/BuiltinsHexagon.td
+++ b/clang/include/clang/Basic/BuiltinsHexagon.td
@@ -996,6 +996,8 @@ def Y2_dccleaninva : HexagonBuiltin<"void(void *)">;
 def Y2_dcfetch : HexagonBuiltin<"void(void *)">;
 def Y2_dcinva : HexagonBuiltin<"void(void *)">;
 def Y2_dczeroa : HexagonBuiltin<"void(void *)">;
+def Y2_icinva : HexagonBuiltin<"void(void *)">;
+def Y2_isync : HexagonBuiltin<"void()">;
 def Y4_l2fetch : HexagonBuiltin<"void(void *, int)">;
 def Y5_l2fetch : HexagonBuiltin<"void(void *, long long int)">;
 
diff --git a/clang/lib/Headers/hexagon_protos.h b/clang/lib/Headers/hexagon_protos.h
index 2642f3c8428d8..d2b0fa7064b05 100644
--- a/clang/lib/Headers/hexagon_protos.h
+++ b/clang/lib/Headers/hexagon_protos.h
@@ -7798,6 +7798,24 @@
 
 #define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa
 
+/* ==========================================================================
+   Assembly Syntax:       icinva(Rs32)
+   C Intrinsic Prototype: void Q6_icinva_A(Address Rs)
+   Instruction Type:      J
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_icinva_A __builtin_HEXAGON_Y2_icinva
+
+/* ==========================================================================
+   Assembly Syntax:       isync
+   C Intrinsic Prototype: void Q6_isync()
+   Instruction Type:      J
+   Execution Slots:       SLOT2
+   ========================================================================== */
+
+#define Q6_isync __builtin_HEXAGON_Y2_isync
+
 /* ==========================================================================
    Assembly Syntax:       l2fetch(Rs32,Rt32)
    C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt)
diff --git a/clang/test/CodeGen/builtins-hexagon.c b/clang/test/CodeGen/builtins-hexagon.c
index 52073f27ae70f..2447aa20b8fc4 100644
--- a/clang/test/CodeGen/builtins-hexagon.c
+++ b/clang/test/CodeGen/builtins-hexagon.c
@@ -1726,6 +1726,10 @@ void test() {
   __builtin_HEXAGON_Y2_dcinva(0);
   // CHECK: @llvm.hexagon.Y2.dczeroa
   __builtin_HEXAGON_Y2_dczeroa(0);
+  // CHECK: @llvm.hexagon.Y2.icinva
+  __builtin_HEXAGON_Y2_icinva(0);
+  // CHECK: @llvm.hexagon.Y2.isync
+  __builtin_HEXAGON_Y2_isync();
   // CHECK: @llvm.hexagon.Y4.l2fetch
   __builtin_HEXAGON_Y4_l2fetch(0, 0);
   // CHECK: @llvm.hexagon.Y5.l2fetch