[clang] [llvm] [RISCV] Remove the experimental XRivosVisni extension (PR #188370)
via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 24 15:59:58 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-llvm-analysis
@llvm/pr-subscribers-clang-driver
Author: Philip Reames (preames)
<details>
<summary>Changes</summary>
---
Patch is 168.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/188370.diff
18 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (-1)
- (modified) llvm/docs/RISCVUsage.rst (-3)
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (-1)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (-7)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-30)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td (+1-86)
- (modified) llvm/lib/Target/RISCV/RISCVInstrPredicates.td (-6)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (-3)
- (modified) llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp (+1-8)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll (-293)
- (modified) llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll (-291)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (-1)
- (modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll (-399)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll (-331)
- (modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3)
- (removed) llvm/test/MC/RISCV/xrivosvisni-valid.s (-43)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (-1)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index b0e82b08f07e0..52334194e18e7 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -255,7 +255,6 @@
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
-// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
// CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b6d3950c56ceb..728ae2dec1ac2 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -537,9 +537,6 @@ The current vendor extensions supported are:
``Xmipslsp``
LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
-``experimental-XRivosVisni``
- LLVM implements `version 0.1 of the Rivos Vector Integer Small New Instructions extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
-
``experimental-XRivosVizip``
LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 52a993decd8c5..30a5d65a901d3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -462,7 +462,6 @@ static constexpr FeatureBitset XCVFeatureGroup = {
RISCV::FeatureVendorXCVbi};
static constexpr FeatureBitset XRivosFeatureGroup = {
- RISCV::FeatureVendorXRivosVisni,
RISCV::FeatureVendorXRivosVizip,
};
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 01ab6054c5e64..6bdc5195801e8 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1670,13 +1670,6 @@ def FeatureVendorXqci
// Rivos Extension(s)
-def FeatureVendorXRivosVisni
- : RISCVExperimentalExtension<0, 1, "Rivos Vector Integer Small New">;
-def HasVendorXRivosVisni
- : Predicate<"Subtarget->hasVendorXRivosVisni()">,
- AssemblerPredicate<(all_of FeatureVendorXRivosVisni),
- "'XRivosVisni' (Rivos Vector Integer Small New)">;
-
def FeatureVendorXRivosVizip
: RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
def HasVendorXRivosVizip
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fbb4e32333e0e..b1641ae34c3e9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10899,13 +10899,6 @@ getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG,
return SmallerVT;
}
-static bool isValidVisniInsertExtractIndex(SDValue Idx) {
- auto *IdxC = dyn_cast<ConstantSDNode>(Idx);
- if (!IdxC || isNullConstant(Idx))
- return false;
- return isUInt<5>(IdxC->getZExtValue());
-}
-
// Custom-legalize INSERT_VECTOR_ELT so that the value is inserted into the
// first position of a vector, and that vector is slid up to the insert index.
// By limiting the active vector length to index+1 and merging with the
@@ -11063,21 +11056,6 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
return convertFromScalableVector(VecVT, Vec, DAG, Subtarget);
}
- // Use ri.vinsert.v.x if available.
- if (Subtarget.hasVendorXRivosVisni() && VecVT.isInteger() &&
- isValidVisniInsertExtractIndex(Idx)) {
- // Tail policy applies to elements past VLMAX (by assumption Idx < VLMAX)
- SDValue PolicyOp =
- DAG.getTargetConstant(RISCVVType::TAIL_AGNOSTIC, DL, XLenVT);
- Vec = DAG.getNode(RISCVISD::RI_VINSERT_VL, DL, ContainerVT, Vec, Val, Idx,
- VL, PolicyOp);
- if (AlignedIdx)
- Vec = DAG.getInsertSubvector(DL, OrigVec, Vec, *AlignedIdx);
- if (!VecVT.isFixedLengthVector())
- return Vec;
- return convertFromScalableVector(VecVT, Vec, DAG, Subtarget);
- }
-
ValInVec = lowerScalarInsert(Val, VL, ContainerVT, DL, DAG, Subtarget);
} else {
// On RV32, i64-element vectors must be specially handled to place the
@@ -11283,14 +11261,6 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
}
}
- // Use ri.vextract.x.v if available.
- // TODO: Avoid index 0 and just use the vmv.x.s
- if (Subtarget.hasVendorXRivosVisni() && EltVT.isInteger() &&
- isValidVisniInsertExtractIndex(Idx)) {
- SDValue Elt = DAG.getNode(RISCVISD::RI_VEXTRACT, DL, XLenVT, Vec, Idx);
- return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt);
- }
-
// If after narrowing, the required slide is still greater than LMUL2,
// fallback to generic expansion and go through the stack. This is done
// for a subtle reason: extracting *all* elements out of a vector is
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 94eccf8dd450c..c6b8fcdf605e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -113,89 +113,4 @@ defm : RIVPatBinaryVL_VV<ri_vzipodd_vl, "PseudoRI_VZIPODD">;
defm : RIVPatBinaryVL_VV<ri_vzip2a_vl, "PseudoRI_VZIP2A">;
defm : RIVPatBinaryVL_VV<ri_vzip2b_vl, "PseudoRI_VZIP2B">;
defm : RIVPatBinaryVL_VV<ri_vunzip2a_vl, "PseudoRI_VUNZIP2A">;
-defm : RIVPatBinaryVL_VV<ri_vunzip2b_vl, "PseudoRI_VUNZIP2B">;
-
-//===----------------------------------------------------------------------===//
-// XRivosVisni
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos",
- mayLoad = false, mayStore = false, hasSideEffects = false,
- ElementsDependOn = EltDepsNone in {
-
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def RI_VZERO : RVInstVUnary<0b000000, 0b00000, OPCFG, (outs VR:$vd),
- (ins), "ri.vzero.v", "$vd"> {
- let vm = 0;
- let vs2 = 0;
-
- let Inst{6-0} = OPC_CUSTOM_2.Value;
-
- let VMConstraint = false;
-}
-
-def RI_VINSERT : CustomRivosVXI<0b010000, OPMVX, (outs VR:$vd_wb),
- (ins VR:$vd, GPR:$rs1, uimm5:$imm),
- "ri.vinsert.v.x", "$vd, $rs1, $imm">;
-
-let ReadsPastVL = 1 in
-def RI_VEXTRACT : CustomRivosXVI<0b010111, OPMVV, (outs GPR:$rd),
- (ins VR:$vs2, uimm5:$imm),
- "ri.vextract.x.v", "$rd, $vs2, $imm">;
-}
-
-// RI_VEXTRACT matches the semantics of ri.vextract.x.v. The result is always
-// XLenVT sign extended from the vector element size. VEXTRACT does *not*
-// have a VL operand.
-def ri_vextract : RVSDNode<"RI_VEXTRACT",
- SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<1>,
- SDTCisInt<2>,
- SDTCisInt<1>]>>;
-
-// RI_VINSERT_VL matches the semantics of ri.vinsert.v.x. It carries a VL operand.
-def ri_vinsert_vl : RVSDNode<"RI_VINSERT_VL",
- SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
- SDTCisInt<0>,
- SDTCisVT<2, XLenVT>,
- SDTCisVT<3, XLenVT>,
- SDTCisVT<4, XLenVT>]>>;
-
-let Predicates = [HasVendorXRivosVisni], mayLoad = 0, mayStore = 0,
- hasSideEffects = 0, HasSEWOp = 1 in
-foreach m = MxList in {
- defvar mx = m.MX;
- let VLMul = m.value in {
- let BaseInstr = RI_VEXTRACT in
- def PseudoRI_VEXTRACT_ # mx :
- RISCVVPseudo<(outs GPR:$rd),
- (ins m.vrclass:$rs2, uimm5:$idx, sew:$sew),
- []>;
-
- let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1,
- Constraints = "$rd = $rs1" in
- def PseudoRI_VINSERT_ # mx :
- RISCVVPseudo<(outs m.vrclass:$rd),
- (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
- sew:$sew, vec_policy:$policy),
- []>;
- }
-}
-
-
-
-foreach vti = AllIntegerVectors in
- let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : Pat<(XLenVT (ri_vextract (vti.Vector vti.RegClass:$vs2), uimm5:$imm)),
- (!cast<Instruction>("PseudoRI_VEXTRACT_" # vti.LMul.MX)
- $vs2, uimm5:$imm, vti.Log2SEW)>;
-
- def : Pat<(vti.Vector (ri_vinsert_vl (vti.Vector vti.RegClass:$merge),
- vti.ScalarRegClass:$rs1,
- uimm5:$imm,
- VLOpFrag,
- (XLenVT timm:$policy))),
- (!cast<Instruction>("PseudoRI_VINSERT_" # vti.LMul.MX)
- $merge, vti.ScalarRegClass:$rs1, uimm5:$imm,
- GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
-
- }
+defm : RIVPatBinaryVL_VV<ri_vunzip2b_vl, "PseudoRI_VUNZIP2B">;
\ No newline at end of file
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 4d6fc05b7316e..bfe8dc9f92d68 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -146,12 +146,6 @@ def isScalarExtractInstr
!instances<Pseudo>("^PseudoVFMV_F.*_S.*")
])>>>;
-def isVExtractInstr
- : TIIPredicate<"isVExtractInstr",
- MCReturnStatement<
- CheckOpcode<
- !instances<Instruction>("^PseudoRI_VEXTRACT.*")>>>;
-
def isScalarInsertInstr
: TIIPredicate<"isScalarInsertInstr",
MCReturnStatement<
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 8f09e25bbfc23..24470300d7229 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2586,9 +2586,6 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(
if (Index == 0)
// We can extract/insert the first element without vslidedown/vslideup.
SlideCost = 0;
- else if (ST->hasVendorXRivosVisni() && isUInt<5>(Index) &&
- Val->getScalarType()->isIntegerTy())
- SlideCost = 0; // With ri.vinsert/ri.vextract there is no slide needed
else if (Opcode == Instruction::InsertElement)
SlideCost = 1; // With a constant index, we do not need to use addi.
}
diff --git a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
index ff2d8b09ed25e..f13b8246662b4 100644
--- a/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
@@ -313,12 +313,6 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
Res.MaskPolicy = false;
}
- if (RISCVInstrInfo::isVExtractInstr(MI)) {
- assert(!RISCVII::hasVLOp(TSFlags));
- // TODO: LMUL can be any larger value (without cost)
- Res.TailPolicy = false;
- }
-
Res.AltFmt = RISCVII::getAltFmtType(MI.getDesc().TSFlags) !=
RISCVII::AltFmtType::DontCare;
Res.TWiden = RISCVII::hasTWidenOp(MI.getDesc().TSFlags) ||
@@ -481,8 +475,7 @@ RISCVVSETVLIInfoAnalysis::computeInfoForInstr(const MachineInstr &MI) const {
InstrInfo.setAVLRegDef(VNI, VLOp.getReg());
}
} else {
- assert(RISCVInstrInfo::isScalarExtractInstr(MI) ||
- RISCVInstrInfo::isVExtractInstr(MI));
+ assert(RISCVInstrInfo::isScalarExtractInstr(MI));
// Pick a random value for state tracking purposes, will be ignored via
// the demanded fields mechanism
InstrInfo.setAVLImm(1);
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
index bca1624d279e7..f3cbe25655a89 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV32V
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV64V
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh,+experimental-xrivosvisni < %s | FileCheck %s --check-prefixes=VISNI
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV32ZVE64X
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV64ZVE64X
; Check that we don't crash querying costs when vectors are not enabled.
@@ -338,170 +337,6 @@ define void @extractelement_int(i32 %x) {
; RV64V-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %nxv16i64_x = extractelement <vscale x 16 x i64> undef, i32 %x
; RV64V-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
-; VISNI-LABEL: 'extractelement_int'
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i1_0 = extractelement <2 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i1_0 = extractelement <4 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i1_0 = extractelement <8 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i1_0 = extractelement <16 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i1_0 = extractelement <32 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv2i1_0 = extractelement <vscale x 2 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv4i1_0 = extractelement <vscale x 4 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %nxv8i1_0 = extractelement <vscale x 8 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %nxv16i1_0 = extractelement <vscale x 16 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %nxv32i1_0 = extractelement <vscale x 32 x i1> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = extractelement <2 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = extractelement <4 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = extractelement <8 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = extractelement <16 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = extractelement <32 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = extractelement <64 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_0 = extractelement <128 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i8_0 = extractelement <vscale x 2 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i8_0 = extractelement <vscale x 4 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i8_0 = extractelement <vscale x 8 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i8_0 = extractelement <vscale x 16 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i8_0 = extractelement <vscale x 32 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i8_0 = extractelement <vscale x 64 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv128i8_0 = extractelement <vscale x 128 x i8> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = extractelement <2 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = extractelement <4 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = extractelement <8 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = extractelement <16 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = extractelement <32 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i16_0 = extractelement <64 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i16_0 = extractelement <vscale x 2 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i16_0 = extractelement <vscale x 4 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i16_0 = extractelement <vscale x 8 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i16_0 = extractelement <vscale x 16 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i16_0 = extractelement <vscale x 32 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv64i16_0 = extractelement <vscale x 64 x i16> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = extractelement <2 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = extractelement <4 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = extractelement <8 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = extractelement <16 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_0 = extractelement <32 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv2i32_0 = extractelement <vscale x 2 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv4i32_0 = extractelement <vscale x 4 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv8i32_0 = extractelement <vscale x 8 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv16i32_0 = extractelement <vscale x 16 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %nxv32i32_0 = extractelement <vscale x 32 x i32> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = extractelement <2 x i64> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = extractelement <4 x i64> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = extractelement <8 x i64> undef, i32 0
-; VISNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i64_0 = extractelement <16 x i64> undef, i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/188370
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