[clang] [llvm] [AArch64][clang][llvm] Add support for Armv9.7-A lookup table intrinsics (PR #187046)

[Jonathan Thackray via cfe-commits]

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@@ -1876,6 +1876,15 @@ let SVETargetGuard = "(sve2|sme2),lut", SMETargetGuard = "sme2,lut" in {
   def SVLUTI4_x2 : SInst<"svluti4_lane[_{d}_x2]", "d2.d[i", "sUshb", MergeNone, "aarch64_sve_luti4_lane_x2", [VerifyRuntimeMode], [ImmCheck<2, ImmCheck0_3>]>;
 }
 
+let SVETargetGuard = "sve2p3", SMETargetGuard = InvalidMode in {
+  def SVLUTI6 : SInst<"svluti6[_{d}]", "d2u", "cUcm", MergeNone, "aarch64_sve_luti6", [IsOverloadNone]>;
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jthackray wrote:

The ACLE says:
```
#### LUTI6

Lookup table read with 6-bit indices (8-bit).

Use of this intrinsic if `svcntb() * 8 < 256` results in undefined behaviour.

```c
  // Variant is  also available for: _u8 _mf8
  svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```
here: https://github.com/ARM-software/acle/pull/428/changes#diff-516526d4a18101dc85300bc2033d0f86dc46c505b7510a7694baabea851aedfaR10039-R10048

So if we think it's wrong, we should adjust the ACLE first.

https://github.com/llvm/llvm-project/pull/187046