[clang] [llvm] [AArch64] Fix _sys implemantation and MRS/MSR Sema checks (PR #187290)

[via cfe-commits]

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@@ -33,33 +33,27 @@ void check__sys(__int64 v) {
   __int64 ret;
 
   __sys(ARM64_DC_CGDSW_EL1, v);
-// CHECK-ASM: msr     S1_0_C7_C10_6, x8
+// CHECK-ASM: sys     #0, c7, c10, #6, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 10, i32 6, i64 %[[VAR]])
 
   __sys(ARM64_IC_IALLU_EL1, v);
-// CHECK-ASM: msr     S1_0_C7_C5_0, x8
+// CHECK-ASM: sys     #0, c7, c5, #0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 5, i32 0, i64 %[[VAR]])
 
   __sys(ARM64_AT_S1E2W, v);
-// CHECK-ASM: msr     S1_4_C7_C8_1, x8
+// CHECK-ASM: at      s1e2w, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 4, i32 7, i32 8, i32 1, i64 %[[VAR]])
 
   __sys(ARM64_TLBI_VMALLE1, v);
-// CHECK-ASM: msr     S1_0_C8_C7_0, x8
+// CHECK-ASM: sys     #0, c8, c7, #0, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 8, i32 7, i32 0, i64 %[[VAR]])
 
   __sys(ARM64_CFP_RCTX, v);
-// CHECK-ASM: msr     S1_3_C7_C3_4, x8
+// CHECK-ASM: sys     #3, c7, c3, #4, x8
 // CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 3, i32 7, i32 3, i32 4, i64 %[[VAR]])
 }
-
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Lukacma wrote:

Yeah, I was more wondering why this kind of assembly is even emitted. I agree that how we handle this in codegen is a separate issue. We can emit valid assembly at O1-3 for __sys(ARM64_TLBI_VMALLE1, 0), but not at O0. I am not sure how big of deal that is. Also the semantics of what should happen in cases like this `  __sys(ARM64_TLBI_VMALLE1, v);` are unclear to me. Though I feel this is beyond the scope of this patch and should be handled separately. 

https://github.com/llvm/llvm-project/pull/187290