[clang] [CIR][AArch64] Upstream vrshrd_n_s64/u64 and vrshr_n_v vector rounding shift right (PR #185992)

[Andrzej Warzyński via cfe-commits]

================
@@ -2781,8 +2827,21 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
   case NEON::BI__builtin_neon_vqshlud_n_s64:
   case NEON::BI__builtin_neon_vqshld_n_u64:
   case NEON::BI__builtin_neon_vqshld_n_s64:
+    cgm.errorNYI(expr->getSourceRange(),
+                 std::string("unimplemented AArch64 builtin call: ") +
+                     getContext().BuiltinInfo.getName(builtinID));
+    return mlir::Value{};
   case NEON::BI__builtin_neon_vrshrd_n_u64:
-  case NEON::BI__builtin_neon_vrshrd_n_s64:
+  case NEON::BI__builtin_neon_vrshrd_n_s64: {
+    // srshl/urshl are left-shift intrinsics; passing -n performs a rounding
+    // right-shift by n.
+    bool isSigned = builtinID == NEON::BI__builtin_neon_vrshrd_n_s64;
----------------
banach-space wrote:

[nit] This `bool` is not required. 
```suggestion
    intrName = builtinID == NEON::BI__builtin_neon_vrshrd_n_s64 ? "aarch64.neon.srshl" : "aarch64.neon.urshl";
```

https://github.com/llvm/llvm-project/pull/185992