[clang] [llvm] [clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a shift operations (PR #186087)

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@@ -2300,6 +2309,15 @@ let SVETargetGuard = InvalidMode, SMETargetGuard = "sme-f16f16" in {
   def SVCVTL_F32_X2 : SInst<"svcvtl_f32[_f16_x2]", "2h", "f", MergeNone, "aarch64_sve_fcvtl_widen_x2", [ IsStreaming],[]>;
 }
 
+//
+// Multi-vector saturating shift right narrow and interleave
+//
+let SVETargetGuard = "sve2p3", SMETargetGuard = "sme2p3" in {
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CarolineConcatto wrote:

Replace:
let SVETargetGuard = "sve2p3", SMETargetGuard = "sme2p3" in {
by
let SVETargetGuard = "sve2p1|sme2", SMETargetGuard = "sve2p1|sme2" in {

https://github.com/llvm/llvm-project/pull/186087