[clang] [CIR][AArch64] Upstream vrshrd_n_s64/u64 and vrshr_n_v vector rounding shift right (PR #185992)

[Andrzej Warzyński via cfe-commits]

https://github.com/banach-space commented:

Thank you for working on this!

Initial scan of the tests implies that we are on the right track 👍🏻  However, this PR is a bit noisy ATM - see my comments inline. I suspect that you have hit some issues when rebasing? There have been a few changes from me recently that might have made that tricky for you. 

Btw, was moving `emitNeonCallToOp` and `emitNeonCall` required? 

https://github.com/llvm/llvm-project/pull/185992