[clang] [CIR][AArch64] add vshr_* builtins (PR #186693)
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Sun Mar 15 11:46:12 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clangir
Author: None (alowqie)
<details>
<summary>Changes</summary>
Part of https://github.com/llvm/llvm-project/issues/185382
- Moved lowering logic from clangir incubator to upstream
- Added tests, partially reusing tests from [neon-intrinsics.c](https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/AArch64/neon-intrinsics.c) and [neon.c](https://github.com/llvm/clangir/blob/main/clang/test/CIR/CodeGen/AArch64/neon.c)
- Made sure that all intrinsics from [Neon ACLE](https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right) are implemented and tested
@<!-- -->banach-space the work on `vshr_*` seemed to involve moving more code from the incubator than I've seen in other PRs, so I'm a bit unsure if I'm correct with this. Those changes made sense to me in order to cover all of `vshr_*` variants but please let me know if I misunderstood something
---
Patch is 25.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/186693.diff
4 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenBuilder.h (+8)
- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+91-3)
- (modified) clang/test/CodeGen/AArch64/neon-intrinsics.c (-191)
- (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+216)
``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h
index 7cd1bdcf491be..82300e66cd50a 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h
+++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h
@@ -432,6 +432,14 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
return cir::ConstantOp::create(*this, loc, getNullMethodAttr(ty));
}
+ cir::ConstantOp getZero(mlir::Location loc, mlir::Type ty) {
+ // TODO: dispatch creation for primitive types.
+ assert((mlir::isa<cir::RecordType>(ty) || mlir::isa<cir::ArrayType>(ty) ||
+ mlir::isa<cir::VectorType>(ty)) &&
+ "NYI for other types");
+ return cir::ConstantOp::create(*this, loc, cir::ZeroAttr::get(ty));
+ }
+
//===--------------------------------------------------------------------===//
// UnaryOp creation helpers
//===--------------------------------------------------------------------===//
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 5534e69b5f8bc..12ac46bdd1b55 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -831,6 +831,69 @@ static cir::VectorType getNeonType(CIRGenFunction *cgf, NeonTypeFlags typeFlags,
llvm_unreachable("Unknown vector element type!");
}
+// Get integer from a mlir::Value that is an int constant or a constant op.
+static int64_t getIntValueFromConstOp(mlir::Value val) {
+ return val.getDefiningOp<cir::ConstantOp>().getIntValue().getSExtValue();
+}
+
+// Build a constant shift amount vector of `vecTy` to shift a vector
+// Here `shitfVal` is a constant integer that will be splated into a
+// a const vector of `vecTy` which is the return of this function
+static mlir::Value emitNeonShiftVector(CIRGenBuilderTy &builder,
+ mlir::Value shiftVal,
+ cir::VectorType vecTy,
+ mlir::Location loc, bool neg) {
+ int shiftAmt = getIntValueFromConstOp(shiftVal);
+ if (neg)
+ shiftAmt = -shiftAmt;
+ llvm::SmallVector<mlir::Attribute> vecAttr{
+ vecTy.getSize(),
+ // ConstVectorAttr requires cir::IntAttr
+ cir::IntAttr::get(vecTy.getElementType(), shiftAmt)};
+ cir::ConstVectorAttr constVecAttr = cir::ConstVectorAttr::get(
+ vecTy, mlir::ArrayAttr::get(builder.getContext(), vecAttr));
+ return cir::ConstantOp::create(builder, loc, constVecAttr);
+}
+
+// Build ShiftOp of vector type whose shift amount is a vector built
+// from a constant integer using `emitNeonShiftVector` function
+static mlir::Value
+emitCommonNeonShift(CIRGenBuilderTy &builder, mlir::Location loc,
+ cir::VectorType resTy, mlir::Value shifTgt,
+ mlir::Value shiftAmt, bool shiftLeft, bool negAmt = false) {
+ shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc, negAmt);
+ return cir::ShiftOp::create(builder, loc, resTy,
+ builder.createBitcast(shifTgt, resTy), shiftAmt,
+ shiftLeft);
+}
+
+// Right-shift a vector by a constant.
+static mlir::Value emitNeonRShiftImm(CIRGenFunction &cgf, mlir::Value shiftVec,
+ mlir::Value shiftVal,
+ cir::VectorType vecTy, bool usgn,
+ mlir::Location loc) {
+ CIRGenBuilderTy &builder = cgf.getBuilder();
+ int64_t shiftAmt = getIntValueFromConstOp(shiftVal);
+ int eltSize =
+ cgf.cgm.getDataLayout().getTypeSizeInBits(vecTy.getElementType());
+
+ shiftVec = builder.createBitcast(shiftVec, vecTy);
+ // lshr/ashr are undefined when the shift amount is equal to the vector
+ // element size.
+ if (shiftAmt == eltSize) {
+ if (usgn) {
+ // Right-shifting an unsigned value by its size yields 0.
+ return builder.getZero(loc, vecTy);
+ }
+ // Right-shifting a signed value by its size is equivalent
+ // to a shift of size-1.
+ --shiftAmt;
+ shiftVal = builder.getConstInt(loc, vecTy.getElementType(), shiftAmt);
+ }
+ return emitCommonNeonShift(builder, loc, vecTy, shiftVec, shiftVal,
+ false /* right shift */);
+}
+
static mlir::Value emitCommonNeonBuiltinExpr(
CIRGenFunction &cgf, unsigned builtinID, unsigned llvmIntrinsic,
unsigned altLLVMIntrinsic, const char *nameHint, unsigned modifier,
@@ -849,6 +912,7 @@ static mlir::Value emitCommonNeonBuiltinExpr(
// Determine the type of this overloaded NEON intrinsic.
NeonTypeFlags neonType(neonTypeConst->getZExtValue());
+ bool isUnsigned = neonType.isUnsigned();
const bool hasLegalHalfType = cgf.getTarget().hasFastHalfType();
// The value of allowBFloatArgsAndRet is true for AArch64, but it should
@@ -1057,8 +1121,13 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vshlq_n_v:
case NEON::BI__builtin_neon_vshll_n_v:
case NEON::BI__builtin_neon_vshrn_n_v:
+ cgf.cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ ctx.BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vshr_n_v:
case NEON::BI__builtin_neon_vshrq_n_v:
+ return emitNeonRShiftImm(cgf, ops[0], ops[1], vTy, isUnsigned, loc);
case NEON::BI__builtin_neon_vst1_v:
case NEON::BI__builtin_neon_vst1q_v:
case NEON::BI__builtin_neon_vst2_v:
@@ -2786,9 +2855,28 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vrsrad_n_u64:
case NEON::BI__builtin_neon_vrsrad_n_s64:
case NEON::BI__builtin_neon_vshld_n_s64:
- case NEON::BI__builtin_neon_vshld_n_u64:
- case NEON::BI__builtin_neon_vshrd_n_s64:
- case NEON::BI__builtin_neon_vshrd_n_u64:
+ case NEON::BI__builtin_neon_vshld_n_u64: {
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ }
+ case NEON::BI__builtin_neon_vshrd_n_s64: {
+ std::optional<llvm::APSInt> amt =
+ expr->getArg(1)->getIntegerConstantExpr(getContext());
+ assert(amt && "Expected argument to be a constant");
+ uint64_t bits = std::min(static_cast<uint64_t>(63), amt->getZExtValue());
+ return builder.createShiftRight(loc, ops[0], bits);
+ }
+ case NEON::BI__builtin_neon_vshrd_n_u64: {
+ std::optional<llvm::APSInt> amt =
+ expr->getArg(1)->getIntegerConstantExpr(getContext());
+ assert(amt && "Expected argument to be a constant");
+ uint64_t shiftAmt = amt->getZExtValue();
+ if (shiftAmt == 64)
+ return builder.getConstInt(loc, builder.getUInt64Ty(), 0);
+ return builder.createShiftRight(loc, ops[0], shiftAmt);
+ }
case NEON::BI__builtin_neon_vsrad_n_s64:
case NEON::BI__builtin_neon_vsrad_n_u64:
case NEON::BI__builtin_neon_vqdmlalh_lane_s16:
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index bfaea2b8ae909..5a95133dd7429 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -6770,166 +6770,6 @@ uint64x2_t test_vshlq_n_u64(uint64x2_t a) {
return vshlq_n_u64(a, 3);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vshr_n_s8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <8 x i8> [[A]], splat (i8 3)
-// CHECK-NEXT: ret <8 x i8> [[VSHR_N]]
-//
-int8x8_t test_vshr_n_s8(int8x8_t a) {
- return vshr_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vshr_n_s16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <4 x i16> [[TMP1]], splat (i16 3)
-// CHECK-NEXT: ret <4 x i16> [[VSHR_N]]
-//
-int16x4_t test_vshr_n_s16(int16x4_t a) {
- return vshr_n_s16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vshr_n_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <2 x i32> [[TMP1]], splat (i32 3)
-// CHECK-NEXT: ret <2 x i32> [[VSHR_N]]
-//
-int32x2_t test_vshr_n_s32(int32x2_t a) {
- return vshr_n_s32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vshrq_n_s8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <16 x i8> [[A]], splat (i8 3)
-// CHECK-NEXT: ret <16 x i8> [[VSHR_N]]
-//
-int8x16_t test_vshrq_n_s8(int8x16_t a) {
- return vshrq_n_s8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vshrq_n_s16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <8 x i16> [[TMP1]], splat (i16 3)
-// CHECK-NEXT: ret <8 x i16> [[VSHR_N]]
-//
-int16x8_t test_vshrq_n_s16(int16x8_t a) {
- return vshrq_n_s16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vshrq_n_s32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 3)
-// CHECK-NEXT: ret <4 x i32> [[VSHR_N]]
-//
-int32x4_t test_vshrq_n_s32(int32x4_t a) {
- return vshrq_n_s32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vshrq_n_s64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <2 x i64> [[TMP1]], splat (i64 3)
-// CHECK-NEXT: ret <2 x i64> [[VSHR_N]]
-//
-int64x2_t test_vshrq_n_s64(int64x2_t a) {
- return vshrq_n_s64(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vshr_n_u8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <8 x i8> [[A]], splat (i8 3)
-// CHECK-NEXT: ret <8 x i8> [[VSHR_N]]
-//
-uint8x8_t test_vshr_n_u8(uint8x8_t a) {
- return vshr_n_u8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vshr_n_u16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <4 x i16> [[TMP1]], splat (i16 3)
-// CHECK-NEXT: ret <4 x i16> [[VSHR_N]]
-//
-uint16x4_t test_vshr_n_u16(uint16x4_t a) {
- return vshr_n_u16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vshr_n_u32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <2 x i32> [[TMP1]], splat (i32 3)
-// CHECK-NEXT: ret <2 x i32> [[VSHR_N]]
-//
-uint32x2_t test_vshr_n_u32(uint32x2_t a) {
- return vshr_n_u32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vshrq_n_u8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <16 x i8> [[A]], splat (i8 3)
-// CHECK-NEXT: ret <16 x i8> [[VSHR_N]]
-//
-uint8x16_t test_vshrq_n_u8(uint8x16_t a) {
- return vshrq_n_u8(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vshrq_n_u16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 3)
-// CHECK-NEXT: ret <8 x i16> [[VSHR_N]]
-//
-uint16x8_t test_vshrq_n_u16(uint16x8_t a) {
- return vshrq_n_u16(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vshrq_n_u32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 3)
-// CHECK-NEXT: ret <4 x i32> [[VSHR_N]]
-//
-uint32x4_t test_vshrq_n_u32(uint32x4_t a) {
- return vshrq_n_u32(a, 3);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vshrq_n_u64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VSHR_N:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 3)
-// CHECK-NEXT: ret <2 x i64> [[VSHR_N]]
-//
-uint64x2_t test_vshrq_n_u64(uint64x2_t a) {
- return vshrq_n_u64(a, 3);
-}
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vsra_n_s8(
// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -17677,37 +17517,6 @@ uint64_t test_vcaltd_f64(float64_t a, float64_t b) {
return (uint64_t)vcaltd_f64(a, b);
}
-// CHECK-LABEL: define dso_local i64 @test_vshrd_n_s64(
-// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SHRD_N:%.*]] = ashr i64 [[A]], 1
-// CHECK-NEXT: ret i64 [[SHRD_N]]
-//
-int64_t test_vshrd_n_s64(int64_t a) {
- return (int64_t)vshrd_n_s64(a, 1);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vshr_n_s64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VSHR_N:%.*]] = ashr <1 x i64> [[TMP1]], splat (i64 1)
-// CHECK-NEXT: ret <1 x i64> [[VSHR_N]]
-//
-int64x1_t test_vshr_n_s64(int64x1_t a) {
- return vshr_n_s64(a, 1);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vshrd_n_u64(
-// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: ret i64 0
-//
-uint64_t test_vshrd_n_u64(uint64_t a) {
- return (uint64_t)vshrd_n_u64(a, 64);
-}
-
// CHECK-LABEL: define dso_local i64 @test_vshrd_n_u64_2(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b740c3b5b2310..be4412f99ab8a 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -936,3 +936,219 @@ uint32x4_t test_vabaq_u32(uint32x4_t v1, uint32x4_t v2, uint32x4_t v3) {
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vabaq_u32(v1, v2, v3);
}
+
+//===------------------------------------------------------===//
+// 2.1.3.2.1 Vector shift right
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vshr_n_s8(
+// CIR-LABEL: @test_vshr_n_s8(
+int8x8_t test_vshr_n_s8(int8x8_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i,
+// CIR-SAME: #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i]> : !cir.vector<8 x !s8i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<8 x !s8i>, [[AMT]] : !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <8 x i8> {{.*}}, splat (i8 3)
+// LLVM: ret <8 x i8> [[VSHR_N]]
+ return vshr_n_s8(a, 3);
+}
+
+// LLVM-LABEL: @test_vshr_n_s16(
+// CIR-LABEL: @test_vshr_n_s16(
+int16x4_t test_vshr_n_s16(int16x4_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s16i, #cir.int<3> : !s16i,
+// CIR-SAME: #cir.int<3> : !s16i, #cir.int<3> : !s16i]> : !cir.vector<4 x !s16i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<4 x !s16i>, [[AMT]] : !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <4 x i16> {{.*}}, splat (i16 3)
+// LLVM: ret <4 x i16> [[VSHR_N]]
+ return vshr_n_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vshr_n_s32(
+// CIR-LABEL: @test_vshr_n_s32(
+int32x2_t test_vshr_n_s32(int32x2_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s32i, #cir.int<3> : !s32i]> : !cir.vector<2 x !s32i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<2 x !s32i>, [[AMT]] : !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <2 x i32> {{.*}}, splat (i32 3)
+// LLVM: ret <2 x i32> [[VSHR_N]]
+ return vshr_n_s32(a, 3);
+}
+
+// LLVM-LABEL: @test_vshr_n_s64(
+// CIR-LABEL: @test_vshr_n_s64(
+int64x1_t test_vshr_n_s64(int64x1_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s64i]> : !cir.vector<1 x !s64i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<1 x !s64i>, [[AMT]] : !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <1 x i64> {{.*}}, splat (i64 3)
+// LLVM: ret <1 x i64> [[VSHR_N]]
+ return vshr_n_s64(a, 3);
+}
+
+// LLVM-LABEL: @test_vshrq_n_s8(
+// CIR-LABEL: @test_vshrq_n_s8(
+int8x16_t test_vshrq_n_s8(int8x16_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i,
+// CIR-SAME: #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i,
+// CIR-SAME: #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i,
+// CIR-SAME: #cir.int<3> : !s8i, #cir.int<3> : !s8i, #cir.int<3> : !s8i]> : !cir.vector<16 x !s8i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<16 x !s8i>, [[AMT]] : !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <16 x i8> {{.*}}, splat (i8 3)
+// LLVM: ret <16 x i8> [[VSHR_N]]
+ return vshrq_n_s8(a, 3);
+}
+
+// LLVM-LABEL: @test_vshrq_n_s16(
+// CIR-LABEL: @test_vshrq_n_s16(
+int16x8_t test_vshrq_n_s16(int16x8_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s16i, #cir.int<3> : !s16i, #cir.int<3> : !s16i,
+// CIR-SAME: #cir.int<3> : !s16i, #cir.int<3> : !s16i, #cir.int<3> : !s16i, #cir.int<3> : !s16i,
+// CIR-SAME: #cir.int<3> : !s16i]> : !cir.vector<8 x !s16i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<8 x !s16i>, [[AMT]] : !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <8 x i16> {{.*}}, splat (i16 3)
+// LLVM: ret <8 x i16> [[VSHR_N]]
+ return vshrq_n_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vshrq_n_s32(
+// CIR-LABEL: @test_vshrq_n_s32(
+int32x4_t test_vshrq_n_s32(int32x4_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s32i, #cir.int<3> : !s32i,
+// CIR-SAME: #cir.int<3> : !s32i, #cir.int<3> : !s32i]> : !cir.vector<4 x !s32i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<4 x !s32i>, [[AMT]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <4 x i32> {{.*}}, splat (i32 3)
+// LLVM: ret <4 x i32> [[VSHR_N]]
+ return vshrq_n_s32(a, 3);
+}
+
+// LLVM-LABEL: @test_vshrq_n_s64(
+// CIR-LABEL: @test_vshrq_n_s64(
+int64x2_t test_vshrq_n_s64(int64x2_t a) {
+// CIR: [[AMT:%.*]] = cir.const #cir.const_vector<[#cir.int<3> : !s64i, #cir.int<3> : !s64i]> : !cir.vector<2 x !s64i>
+// CIR: {{%.*}} = cir.shift(right, {{%.*}} : !cir.vector<2 x !s64i>, [[AMT]] : !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i>
+
+// LLVM: [[VSHR_N:%.*]] = ashr <2 x i64> {{.*}}, splat (i64 3)
+// LLVM: ret <2 x i64> [[VSHR_N]]
+ return vshrq_n_s64(a, 3);
+}
+
+// LLVM...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/186693
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