[clang] c389129 - [RISCV] Add more extensions to spacemit-x100 (#186351)
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cfe-commits at lists.llvm.org
Sat Mar 14 07:47:42 PDT 2026
Author: Mark Zhuang
Date: 2026-03-14T22:47:36+08:00
New Revision: c389129bcf84ef069794db844dcd92d144222af6
URL: https://github.com/llvm/llvm-project/commit/c389129bcf84ef069794db844dcd92d144222af6
DIFF: https://github.com/llvm/llvm-project/commit/c389129bcf84ef069794db844dcd92d144222af6.diff
LOG: [RISCV] Add more extensions to spacemit-x100 (#186351)
Added:
Modified:
clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c
llvm/lib/Target/RISCV/RISCVProcessors.td
Removed:
################################################################################
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c
index e1d7ac6f2d781..8c814cfbdf8a6 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c
@@ -12,6 +12,7 @@
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
+// CHECK-NEXT: h 1.0 'H' (Hypervisor)
// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes)
// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions)
// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
@@ -23,6 +24,7 @@
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
+// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters)
@@ -75,9 +77,34 @@
// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256)
// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
+// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
+// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
+// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
+// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
+// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp)
+// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)
+// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
+// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
+// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
+// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
+// CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads)
+// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
+// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
+// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
+// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
+// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
+// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
+// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values)
+// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode)
+// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported)
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
+// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
+// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported)
+// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
+// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
+// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
// CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkc1p0_zbs1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_supm1p0_xsmtvdot1p0
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkc1p0_zbs1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_smepmp1p0_smnpm1p0_smstateen1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_sspm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_xsmtvdot1p0
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 74b1fad703989..bc376c4940d22 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -811,8 +811,12 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
def SPACEMIT_X100 : RISCVProcessorModel<"spacemit-x100",
SpacemitX100Model,
- !listconcat(RVA23U64Features,
- [FeatureStdExtZbc,
+ !listconcat(RVA23S64Features,
+ [FeatureStdExtSmepmp,
+ FeatureStdExtSmnpm,
+ FeatureStdExtSmstateen,
+ FeatureStdExtSspm,
+ FeatureStdExtZbc,
FeatureStdExtZbkc,
FeatureStdExtZfbfmin,
FeatureStdExtZfh,
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