[clang] [RISCV][NFC] Move extension test for spacemit-x60 to a separate file (PR #186357)

via cfe-commits cfe-commits at lists.llvm.org
Fri Mar 13 03:13:01 PDT 2026


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-clang

Author: Mark Zhuang (zqb-all)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/186357.diff


2 Files Affected:

- (added) clang/test/Driver/print-enabled-extensions/riscv-spacemit-x60.c (+70) 
- (modified) clang/test/Driver/riscv-cpus.c (+5-54) 


``````````diff
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x60.c b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x60.c
new file mode 100644
index 0000000000000..b2cdf2d0e58c1
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x60.c
@@ -0,0 +1,70 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang --target=riscv64 -mcpu=spacemit-x60 --print-enabled-extensions | FileCheck %s
+
+// CHECK: Extensions enabled for the given RISC-V target
+// CHECK-EMPTY:
+// CHECK-NEXT:     Name                 Version   Description
+// CHECK-NEXT:     i                    2.1       'I' (Base Integer Instruction Set)
+// CHECK-NEXT:     m                    2.0       'M' (Integer Multiplication and Division)
+// CHECK-NEXT:     a                    2.1       'A' (Atomic Instructions)
+// CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
+// CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
+// CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
+// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
+// CHECK-NEXT:     v                    1.0       'V' (Vector Extension for Application Processors)
+// CHECK-NEXT:     zic64b               1.0       'Zic64b' (Cache Block Size Is 64 Bytes)
+// CHECK-NEXT:     zicbom               1.0       'Zicbom' (Cache-Block Management Instructions)
+// CHECK-NEXT:     zicbop               1.0       'Zicbop' (Cache-Block Prefetch Instructions)
+// CHECK-NEXT:     zicboz               1.0       'Zicboz' (Cache-Block Zero Instructions)
+// CHECK-NEXT:     ziccamoa             1.0       'Ziccamoa' (Main Memory Supports All Atomics in A)
+// CHECK-NEXT:     ziccif               1.0       'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
+// CHECK-NEXT:     zicclsm              1.0       'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
+// CHECK-NEXT:     ziccrse              1.0       'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
+// CHECK-NEXT:     zicntr               2.0       'Zicntr' (Base Counters and Timers)
+// CHECK-NEXT:     zicond               1.0       'Zicond' (Integer Conditional Operations)
+// CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
+// CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
+// CHECK-NEXT:     zihintpause          2.0       'Zihintpause' (Pause Hint)
+// CHECK-NEXT:     zihpm                2.0       'Zihpm' (Hardware Performance Counters)
+// CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
+// CHECK-NEXT:     za64rs               1.0       'Za64rs' (Reservation Set Size of at Most 64 Bytes)
+// CHECK-NEXT:     zaamo                1.0       'Zaamo' (Atomic Memory Operations)
+// CHECK-NEXT:     zalrsc               1.0       'Zalrsc' (Load-Reserved/Store-Conditional)
+// CHECK-NEXT:     zfh                  1.0       'Zfh' (Half-Precision Floating-Point)
+// CHECK-NEXT:     zfhmin               1.0       'Zfhmin' (Half-Precision Floating-Point Minimal)
+// CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
+// CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
+// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
+// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
+// CHECK-NEXT:     zbc                  1.0       'Zbc' (Carry-Less Multiplication)
+// CHECK-NEXT:     zbkc                 1.0       'Zbkc' (Carry-less multiply instructions for Cryptography)
+// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT:     zkt                  1.0       'Zkt' (Data Independent Execution Latency)
+// CHECK-NEXT:     zve32f               1.0       'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
+// CHECK-NEXT:     zve32x               1.0       'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
+// CHECK-NEXT:     zve64d               1.0       'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
+// CHECK-NEXT:     zve64f               1.0       'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
+// CHECK-NEXT:     zve64x               1.0       'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
+// CHECK-NEXT:     zvfh                 1.0       'Zvfh' (Vector Half-Precision Floating-Point)
+// CHECK-NEXT:     zvfhmin              1.0       'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
+// CHECK-NEXT:     zvkt                 1.0       'Zvkt' (Vector Data-Independent Execution Latency)
+// CHECK-NEXT:     zvl128b              1.0       'Zvl128b' (Minimum Vector Length 128)
+// CHECK-NEXT:     zvl256b              1.0       'Zvl256b' (Minimum Vector Length 256)
+// CHECK-NEXT:     zvl32b               1.0       'Zvl32b' (Minimum Vector Length 32)
+// CHECK-NEXT:     zvl64b               1.0       'Zvl64b' (Minimum Vector Length 64)
+// CHECK-NEXT:     ssccptr              1.0       'Ssccptr' (Main memory supports page table reads)
+// CHECK-NEXT:     sscofpmf             1.0       'Sscofpmf' (Count Overflow and Mode-Based Filtering)
+// CHECK-NEXT:     sscounterenw         1.0       'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
+// CHECK-NEXT:     sstc                 1.0       'Sstc' (Supervisor-mode timer interrupts)
+// CHECK-NEXT:     sstvala              1.0       'Sstvala' (stval provides all needed values)
+// CHECK-NEXT:     sstvecd              1.0       'Sstvecd' (stvec supports Direct mode)
+// CHECK-NEXT:     svade                1.0       'Svade' (Raise exceptions on improper A/D bits)
+// CHECK-NEXT:     svbare               1.0       'Svbare' (satp mode Bare supported)
+// CHECK-NEXT:     svinval              1.0       'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
+// CHECK-NEXT:     svnapot              1.0       'Svnapot' (NAPOT Translation Contiguity)
+// CHECK-NEXT:     svpbmt               1.0       'Svpbmt' (Page-Based Memory Types)
+// CHECK-NEXT:     xsmtvdot             1.0       'XSMTVDot' (SpacemiT Vector Dot Product Extension)
+// CHECK-EMPTY:
+// CHECK-NEXT: Experimental extensions
+// CHECK-EMPTY:
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbkc1p0_zbs1p0_zkt1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvkt1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_xsmtvdot1p0
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 64b8cc27974fd..e33512a3d66aa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -112,62 +112,13 @@
 // MTUNE-SPACEMIT-A100: "-tune-cpu" "spacemit-a100"
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
-// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
-// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+xsmtvdot"
+// MCPU-SPACEMIT-X60: "-target-cpu" "spacemit-x60"
+// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-spacemit-x60.c`
 // MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=spacemit-x60 | FileCheck -check-prefix=MTUNE-SPACEMIT-X60 %s
+// MTUNE-SPACEMIT-X60: "-tune-cpu" "spacemit-x60"
+
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x100 | FileCheck -check-prefix=MCPU-SPACEMIT-X100 %s
 // MCPU-SPACEMIT-X100: "-target-cpu" "spacemit-x100"
 // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-spacemit-x100.c`

``````````

</details>


https://github.com/llvm/llvm-project/pull/186357


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