[clang] [CIR][RISCV][NFC] Add CIRGenBuiltinRISCV file to support RISCV builtins codegen (PR #186050)
Jianjian Guan via cfe-commits
cfe-commits at lists.llvm.org
Fri Mar 13 00:01:59 PDT 2026
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/186050
>From aa74996708ad838e72b25d3c30eeba0461a15861 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Thu, 12 Mar 2026 15:27:42 +0800
Subject: [PATCH 1/2] [CIR][RISCV][NFC] Add CIRGenBuiltinRISCV file to support
RISCV builtins codegen
---
clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp | 5 +-
clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 103 +++++++++++++++++++
clang/lib/CIR/CodeGen/CIRGenFunction.h | 3 +
clang/lib/CIR/CodeGen/CMakeLists.txt | 1 +
4 files changed, 110 insertions(+), 2 deletions(-)
create mode 100644 clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
index e9a8768e8213f..a0277ef993e7b 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
@@ -2362,11 +2362,12 @@ emitTargetArchBuiltinExpr(CIRGenFunction *cgf, unsigned builtinID,
case llvm::Triple::wasm32:
case llvm::Triple::wasm64:
case llvm::Triple::hexagon:
- case llvm::Triple::riscv32:
- case llvm::Triple::riscv64:
// These are actually NYI, but that will be reported by emitBuiltinExpr.
// At this point, we don't even know that the builtin is target-specific.
return std::nullopt;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+ return cgf->emitRISCVBuiltinExpr(builtinID, e);
default:
return std::nullopt;
}
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
new file mode 100644
index 0000000000000..f5cfadc4411d0
--- /dev/null
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -0,0 +1,103 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This contains code to emit RISC-V Builtin calls as CIR or a function call
+// to be later resolved.
+//
+//===----------------------------------------------------------------------===//
+
+#include "CIRGenFunction.h"
+#include "clang/Basic/TargetBuiltins.h"
+
+using namespace clang;
+using namespace clang::CIRGen;
+
+std::optional<mlir::Value>
+CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
+ switch (builtinID) {
+ default:
+ return std::nullopt;
+
+ // Zihintpause
+ case RISCV::BI__builtin_riscv_pause:
+ // Zihintntl
+ case RISCV::BI__builtin_riscv_ntl_load:
+ case RISCV::BI__builtin_riscv_ntl_store:
+ // Zbb
+ case RISCV::BI__builtin_riscv_orc_b_32:
+ case RISCV::BI__builtin_riscv_orc_b_64:
+ case RISCV::BI__builtin_riscv_clz_32:
+ case RISCV::BI__builtin_riscv_clz_64:
+ case RISCV::BI__builtin_riscv_ctz_32:
+ case RISCV::BI__builtin_riscv_ctz_64:
+ // Zbc
+ case RISCV::BI__builtin_riscv_clmul_32:
+ case RISCV::BI__builtin_riscv_clmul_64:
+ case RISCV::BI__builtin_riscv_clmulh_32:
+ case RISCV::BI__builtin_riscv_clmulh_64:
+ case RISCV::BI__builtin_riscv_clmulr_32:
+ case RISCV::BI__builtin_riscv_clmulr_64:
+ // Zbkb
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
+ case RISCV::BI__builtin_riscv_zip_32:
+ case RISCV::BI__builtin_riscv_unzip_32:
+ // Zbkx
+ case RISCV::BI__builtin_riscv_xperm4_32:
+ case RISCV::BI__builtin_riscv_xperm4_64:
+ case RISCV::BI__builtin_riscv_xperm8_32:
+ case RISCV::BI__builtin_riscv_xperm8_64:
+ // Zknh
+ case RISCV::BI__builtin_riscv_sha256sig0:
+ case RISCV::BI__builtin_riscv_sha256sig1:
+ case RISCV::BI__builtin_riscv_sha256sum0:
+ case RISCV::BI__builtin_riscv_sha256sum1:
+ // Zksed
+ case RISCV::BI__builtin_riscv_sm4ks:
+ case RISCV::BI__builtin_riscv_sm4ed:
+ // Zksh
+ case RISCV::BI__builtin_riscv_sm3p0:
+ case RISCV::BI__builtin_riscv_sm3p1:
+ // XCValu
+ case RISCV::BI__builtin_riscv_cv_alu_addN:
+ case RISCV::BI__builtin_riscv_cv_alu_addRN:
+ case RISCV::BI__builtin_riscv_cv_alu_adduN:
+ case RISCV::BI__builtin_riscv_cv_alu_adduRN:
+ case RISCV::BI__builtin_riscv_cv_alu_clip:
+ case RISCV::BI__builtin_riscv_cv_alu_clipu:
+ case RISCV::BI__builtin_riscv_cv_alu_extbs:
+ case RISCV::BI__builtin_riscv_cv_alu_extbz:
+ case RISCV::BI__builtin_riscv_cv_alu_exths:
+ case RISCV::BI__builtin_riscv_cv_alu_exthz:
+ case RISCV::BI__builtin_riscv_cv_alu_sle:
+ case RISCV::BI__builtin_riscv_cv_alu_sleu:
+ case RISCV::BI__builtin_riscv_cv_alu_subN:
+ case RISCV::BI__builtin_riscv_cv_alu_subRN:
+ case RISCV::BI__builtin_riscv_cv_alu_subuN:
+ case RISCV::BI__builtin_riscv_cv_alu_subuRN:
+ // XAndesPerf
+ case RISCV::BI__builtin_riscv_nds_ffb_32:
+ case RISCV::BI__builtin_riscv_nds_ffb_64:
+ case RISCV::BI__builtin_riscv_nds_ffzmism_32:
+ case RISCV::BI__builtin_riscv_nds_ffzmism_64:
+ case RISCV::BI__builtin_riscv_nds_ffmism_32:
+ case RISCV::BI__builtin_riscv_nds_ffmism_64:
+ case RISCV::BI__builtin_riscv_nds_flmism_32:
+ case RISCV::BI__builtin_riscv_nds_flmism_64:
+ // XAndesBFHCvt
+ case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
+ case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s: {
+ cgm.errorNYI(e->getSourceRange(),
+ std::string("unimplemented RISC-V builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ }
+
+ // TODO: Handle vector builtins in tablegen.
+ }
+}
diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.h b/clang/lib/CIR/CodeGen/CIRGenFunction.h
index 1b3518616d6b7..8e15a5fd35117 100644
--- a/clang/lib/CIR/CodeGen/CIRGenFunction.h
+++ b/clang/lib/CIR/CodeGen/CIRGenFunction.h
@@ -1935,6 +1935,9 @@ class CIRGenFunction : public CIRGenTypeCache {
mlir::LogicalResult emitWhileStmt(const clang::WhileStmt &s);
+ std::optional<mlir::Value> emitRISCVBuiltinExpr(unsigned builtinID,
+ const CallExpr *expr);
+
std::optional<mlir::Value> emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr);
diff --git a/clang/lib/CIR/CodeGen/CMakeLists.txt b/clang/lib/CIR/CodeGen/CMakeLists.txt
index f982fcf5b1b8a..81d95dda2ec9e 100644
--- a/clang/lib/CIR/CodeGen/CMakeLists.txt
+++ b/clang/lib/CIR/CodeGen/CMakeLists.txt
@@ -14,6 +14,7 @@ add_clang_library(clangCIR
CIRGenBuiltin.cpp
CIRGenBuiltinAArch64.cpp
CIRGenBuiltinAMDGPU.cpp
+ CIRGenBuiltinRISCV.cpp
CIRGenBuiltinX86.cpp
CIRGenCall.cpp
CIRGenClass.cpp
>From 8212fad3f9fd4158e4b573caf4c6c0c61bcc1d1b Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Fri, 13 Mar 2026 15:01:34 +0800
Subject: [PATCH 2/2] Address comment
---
clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 39 ++++++++++++--------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index f5cfadc4411d0..899ba253be7c9 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -19,22 +19,21 @@ using namespace clang::CIRGen;
std::optional<mlir::Value>
CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
+ if (builtinID == Builtin::BI__builtin_cpu_supports ||
+ builtinID == Builtin::BI__builtin_cpu_init ||
+ builtinID == Builtin::BI__builtin_cpu_is) {
+ cgm.errorNYI(e->getSourceRange(),
+ std::string("unimplemented RISC-V builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+ }
switch (builtinID) {
default:
- return std::nullopt;
+ llvm_unreachable("unexpected builtin ID");
- // Zihintpause
- case RISCV::BI__builtin_riscv_pause:
- // Zihintntl
- case RISCV::BI__builtin_riscv_ntl_load:
- case RISCV::BI__builtin_riscv_ntl_store:
// Zbb
case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64:
- case RISCV::BI__builtin_riscv_clz_32:
- case RISCV::BI__builtin_riscv_clz_64:
- case RISCV::BI__builtin_riscv_ctz_32:
- case RISCV::BI__builtin_riscv_ctz_64:
// Zbc
case RISCV::BI__builtin_riscv_clmul_32:
case RISCV::BI__builtin_riscv_clmul_64:
@@ -42,16 +41,16 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
case RISCV::BI__builtin_riscv_clmulh_64:
case RISCV::BI__builtin_riscv_clmulr_32:
case RISCV::BI__builtin_riscv_clmulr_64:
- // Zbkb
- case RISCV::BI__builtin_riscv_brev8_32:
- case RISCV::BI__builtin_riscv_brev8_64:
- case RISCV::BI__builtin_riscv_zip_32:
- case RISCV::BI__builtin_riscv_unzip_32:
// Zbkx
case RISCV::BI__builtin_riscv_xperm4_32:
case RISCV::BI__builtin_riscv_xperm4_64:
case RISCV::BI__builtin_riscv_xperm8_32:
case RISCV::BI__builtin_riscv_xperm8_64:
+ // Zbkb
+ case RISCV::BI__builtin_riscv_brev8_32:
+ case RISCV::BI__builtin_riscv_brev8_64:
+ case RISCV::BI__builtin_riscv_zip_32:
+ case RISCV::BI__builtin_riscv_unzip_32:
// Zknh
case RISCV::BI__builtin_riscv_sha256sig0:
case RISCV::BI__builtin_riscv_sha256sig1:
@@ -63,6 +62,16 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
// Zksh
case RISCV::BI__builtin_riscv_sm3p0:
case RISCV::BI__builtin_riscv_sm3p1:
+ // Zbb
+ case RISCV::BI__builtin_riscv_clz_32:
+ case RISCV::BI__builtin_riscv_clz_64:
+ case RISCV::BI__builtin_riscv_ctz_32:
+ case RISCV::BI__builtin_riscv_ctz_64:
+ // Zihintntl
+ case RISCV::BI__builtin_riscv_ntl_load:
+ case RISCV::BI__builtin_riscv_ntl_store:
+ // Zihintpause
+ case RISCV::BI__builtin_riscv_pause:
// XCValu
case RISCV::BI__builtin_riscv_cv_alu_addN:
case RISCV::BI__builtin_riscv_cv_alu_addRN:
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