[clang] [CIR][AArch64] Lower BF16 vduph lane builtins (PR #185852)

[Jiahao Guo via cfe-commits]

E00N777 wrote:

> Thanks for the updates! I've left some requests inline. I also have a high-level question - have you considered the other variants in https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-all-lanes-to-the-same-value-2 ?

@banach-space 
Thank you very much for your patience and guidance. To make sure I do not make the same mistakes again, I’d like to summarize the changes I believe I need to make and confirm that I’ve understood them correctly:

1 I should replace builder.createExtractElement with cir::VecExtractOp::create in the lowering.

2 I should restore the original case order in the switch statement, avoid reordering cases for shared logic, and limit the implementation scope to only these two builtins:
NEON::BI__builtin_neon_vduph_lane_bf16
NEON::BI__builtin_neon_vduph_laneq_bf16

3 The tests should use the ACLE intrinsics (vduph_lane_bf16 / vduph_laneq_bf16) rather than testing the builtin interface directly.

4 I should rename the current test file from clang/test/CodeGen/AArch64/neon/bf16-vduph.c to clang/test/CodeGen/AArch64/neon/bf16-getset.c, and move the corresponding ACLE tests from clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c into that new file.

5 After porting those tests, I should remove the migrated cases from the old file, keep the new file in the neon/ test style (LLVM-LABEL / CIR-LABEL with inline // CIR: / // LLVM: checks), and preserve the existing LLVM expectations from the old test as much as possible.

https://github.com/llvm/llvm-project/pull/185852