[clang] [llvm] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (PR #184566)

[via cfe-commits]

https://github.com/joshua-arch1 updated https://github.com/llvm/llvm-project/pull/184566

>From 8835ba83e952d9508a6c38c19a93ee4c80399f2a Mon Sep 17 00:00:00 2001
From: joshua-arch1 <cooper.joshua at linux.alibaba.com>
Date: Thu, 5 Mar 2026 14:22:25 +0800
Subject: [PATCH] [RISCV] Support 'f' Inline Assembly Constraint for bfloat16

---
 clang/test/CodeGen/RISCV/riscv-inline-asm.c   |  4 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |  4 ++
 .../RISCV/inline-asm-bf-constraint-f.ll       | 45 +++++++++++++++++++
 3 files changed, 53 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll

diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
index f2031e0adcbcb..183ee7e34764c 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
@@ -78,6 +78,7 @@ void test_K(void) {
 
 float f;
 double d;
+__bf16 bf;
 void test_f(void) {
 // CHECK-LABEL: define{{.*}} void @test_f()
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, ptr @f
@@ -86,6 +87,9 @@ void test_f(void) {
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, ptr @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load bfloat, ptr @bf
+// CHECK: call void asm sideeffect "", "f"(bfloat [[FLT_ARG]])
+  asm volatile ("" :: "f"(bf));
 }
 
 void test_A(int *p) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7e62957529fea..48c73e92fd7be 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -25215,6 +25215,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           return std::make_pair(0U, &RISCV::FPR16RegClass);
         if (Subtarget.hasStdExtZhinxmin())
           return std::make_pair(0U, &RISCV::GPRF16NoX0RegClass);
+      } else if (VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
+        return std::make_pair(0U, &RISCV::FPR16RegClass);
       } else if (VT == MVT::f32) {
         if (Subtarget.hasStdExtF())
           return std::make_pair(0U, &RISCV::FPR32RegClass);
@@ -25312,6 +25314,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &RISCV::FPR16CRegClass);
       if (Subtarget.hasStdExtZhinxmin())
         return std::make_pair(0U, &RISCV::GPRF16CRegClass);
+    } else if (VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
+      return std::make_pair(0U, &RISCV::FPR16CRegClass);
     } else if (VT == MVT::f32) {
       if (Subtarget.hasStdExtF())
         return std::make_pair(0U, &RISCV::FPR32CRegClass);
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll
new file mode 100644
index 0000000000000..923a0ab7bc767
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-bf-constraint-f.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin,+zfh -target-abi=ilp32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32FZFBFMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin,+zfh -target-abi=lp64f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64FZFBFMIN %s
+
+define bfloat @constraint_f_bfloat(float %a) nounwind {
+; RV32FZFBFMIN-LABEL: constraint_f_bfloat:
+; RV32FZFBFMIN:       # %bb.0:
+; RV32FZFBFMIN-NEXT:    fmv.w.x fa5, a0
+; RV32FZFBFMIN-NEXT:    #APP
+; RV32FZFBFMIN-NEXT:    fcvt.bf16.s fa5, fa5
+; RV32FZFBFMIN-NEXT:    #NO_APP
+; RV32FZFBFMIN-NEXT:    fmv.x.h a0, fa5
+; RV32FZFBFMIN-NEXT:    ret
+;
+; RV64FZFBFMIN-LABEL: constraint_f_bfloat:
+; RV64FZFBFMIN:       # %bb.0:
+; RV64FZFBFMIN-NEXT:    #APP
+; RV64FZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
+; RV64FZFBFMIN-NEXT:    #NO_APP
+; RV64FZFBFMIN-NEXT:    ret
+  %1 = tail call bfloat asm "fcvt.bf16.s $0, $1", "=f,f"(float %a)
+  ret bfloat %1
+}
+
+define bfloat @constraint_cf_bfloat(float %a) nounwind {
+; RV32FZFBFMIN-LABEL: constraint_cf_bfloat:
+; RV32FZFBFMIN:       # %bb.0:
+; RV32FZFBFMIN-NEXT:    fmv.w.x fa5, a0
+; RV32FZFBFMIN-NEXT:    #APP
+; RV32FZFBFMIN-NEXT:    fcvt.bf16.s fa5, fa5
+; RV32FZFBFMIN-NEXT:    #NO_APP
+; RV32FZFBFMIN-NEXT:    fmv.x.h a0, fa5
+; RV32FZFBFMIN-NEXT:    ret
+;
+; RV64FZFBFMIN-LABEL: constraint_cf_bfloat:
+; RV64FZFBFMIN:       # %bb.0:
+; RV64FZFBFMIN-NEXT:    #APP
+; RV64FZFBFMIN-NEXT:    fcvt.bf16.s fa0, fa0
+; RV64FZFBFMIN-NEXT:    #NO_APP
+; RV64FZFBFMIN-NEXT:    ret
+  %1 = tail call bfloat asm "fcvt.bf16.s $0, $1", "=^cf,^cf"(float %a)
+  ret bfloat %1
+}