[clang] [Clang] Fix clang crash for fopenmp statement(for) inside lambda function (PR #146772)
Shivam Gupta via cfe-commits
cfe-commits at lists.llvm.org
Mon Mar 2 01:37:32 PST 2026
https://github.com/xgupta updated https://github.com/llvm/llvm-project/pull/146772
>From 8037bf2283d200beec0e8eca0916a570c1b1d470 Mon Sep 17 00:00:00 2001
From: Shivam Gupta <shivam98.tkg at gmail.com>
Date: Wed, 2 Jul 2025 18:07:19 +0530
Subject: [PATCH 1/2] [Clang] Fix clang crash for fopenmp statement(parallel
for) inside lambda function
Previously, implicit variable like `__begin3` used in range-based
OpenMP for-loops were not being properly privatized, leading to
missing entries in LocalDeclMap and crashes.
This patch ensures such implicit loop counters are handled in
`EmitOMPPrivateLoopCounters` by allocating memory and registering
them in the local declaration map before loop codegen.
This fixes #PR146335
---
clang/lib/CodeGen/CGStmtOpenMP.cpp | 6 +
clang/test/OpenMP/for_range_loop_codegen.cpp | 419 +++++++++++++++++++
2 files changed, 425 insertions(+)
create mode 100644 clang/test/OpenMP/for_range_loop_codegen.cpp
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index ea89db5471089..239914418cade 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -2395,6 +2395,12 @@ void CodeGenFunction::EmitOMPPrivateLoopCounters(
for (const Expr *E : S.counters()) {
const auto *VD = cast<VarDecl>(cast<DeclRefExpr>(E)->getDecl());
const auto *PrivateVD = cast<VarDecl>(cast<DeclRefExpr>(*I)->getDecl());
+ // Privatize original counter variable (e.g., __beginN, __endN, __rangeN)
+ if (!LocalDeclMap.count(VD)) {
+ Address Addr = CreateMemTemp(VD->getType(), VD->getName());
+ LocalDeclMap.insert({VD, Addr});
+ (void)LoopScope.addPrivate(VD, Addr);
+ }
// Emit var without initialization.
AutoVarEmission VarEmission = EmitAutoVarAlloca(*PrivateVD);
EmitAutoVarCleanups(VarEmission);
diff --git a/clang/test/OpenMP/for_range_loop_codegen.cpp b/clang/test/OpenMP/for_range_loop_codegen.cpp
new file mode 100644
index 0000000000000..bc86c7a477210
--- /dev/null
+++ b/clang/test/OpenMP/for_range_loop_codegen.cpp
@@ -0,0 +1,419 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --clang-args ['-fopenmp', '-std=c++20'] --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
+// RUN: %clang_cc1 -verify -fopenmp -std=c++20 -emit-llvm %s -o - | FileCheck %s
+// expected-no-diagnostics
+#ifndef HEADER
+#define HEADER
+
+enum a {};
+class b {
+public:
+ b(int);
+};
+struct c {
+ typedef b h;
+};
+using e = b;
+using f = b;
+template <typename> class g {};
+template <typename l> class i {
+public:
+ using j = long;
+ l::h aa;
+ i(g<l>) : aa{0} {}
+ bool operator!=(i);
+ void operator++();
+ auto operator*() {
+ int k;
+ return k;
+ }
+ j operator-(i);
+ void operator+=(j);
+};
+class o : public g<c> {
+public:
+ using p = int;
+ o(p, e, f);
+};
+// CHECK1-LABEL: @_Z5begin1gI1cE(
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
+// CHECK1-NEXT: [[AC:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G]], align 1
+// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AC]], i32 0, i32 0
+// CHECK1-NEXT: store i8 [[AC_COERCE:%.*]], ptr [[COERCE_DIVE]], align 1
+// CHECK1-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
+// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[RETVAL]], i8 [[TMP0]])
+// CHECK1-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
+// CHECK1-NEXT: ret i8 [[TMP1]]
+auto begin(g<c> ac) {
+ i ad(ac);
+ return ad;
+}
+template <typename l> auto end(l ac) {
+ i ad(ac);
+ return ad;
+}
+using m = b;
+using n = b;
+class D {
+protected:
+ D(int, int, n, m, a);
+};
+class H : D {
+ int af;
+ o t;
+
+public:
+ a v;
+ int q;
+// CHECK1-LABEL: @_ZN1HC1E1bS0_(
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
+// CHECK1-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
+// CHECK1-NEXT: store i8 [[AG_COERCE:%.*]], ptr [[COERCE_DIVE]], align 1
+// CHECK1-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
+// CHECK1-NEXT: store i8 [[R_COERCE:%.*]], ptr [[COERCE_DIVE1]], align 1
+// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[COERCE_DIVE3:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE3]], align 1
+// CHECK1-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1HC2E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[THIS2]], i8 [[TMP0]], i8 [[TMP1]])
+// CHECK1-NEXT: ret ptr [[THIS2]]
+ H(n ag, m r) : D(0, 0, ag, r, a{}), af(0), t{o(0, 0, 0)}, q(0), v() {}
+// CHECK1-LABEL: @_ZN1H1sEv(
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[THIS1]], i64 4
+// CHECK1-NEXT: ret void
+ auto s() { return t; }
+};
+template <typename> class F { void ak(H &) const; };
+template <typename am> void F<am>::ak(H &an) const {
+ auto ao = an.s();
+ auto ap = [ao](H) {
+#pragma omp for
+ for (auto d : ao)
+ ;
+ };
+ H ar(0, 0);
+ ap(ar);
+}
+// CHECK1-LABEL: @_ZNK1FIdE2akER1H(
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[AN_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[AO:%.*]] = alloca [[CLASS_O:%.*]], align 1
+// CHECK1-NEXT: [[UNDEF_AGG_TMP:%.*]] = alloca [[CLASS_O]], align 1
+// CHECK1-NEXT: [[AP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// CHECK1-NEXT: [[AR:%.*]] = alloca [[CLASS_H:%.*]], align 4
+// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B:%.*]], align 1
+// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_H]], align 4
+// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: store ptr [[AN:%.*]], ptr [[AN_ADDR]], align 8
+// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AN_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
+// CHECK1-NEXT: call void @_ZN1H1sEv(ptr noundef nonnull align 4 dereferenceable(16) [[TMP0]])
+// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP]], i32 noundef 0)
+// CHECK1-NEXT: [[CALL3:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP2]], i32 noundef 0)
+// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
+// CHECK1-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP2]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK1-NEXT: [[CALL5:%.*]] = call noundef ptr @_ZN1HC1E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[AR]], i8 [[TMP1]], i8 [[TMP2]])
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP6]], ptr align 4 [[AR]], i64 16, i1 false)
+// CHECK1-NEXT: [[TMP3:%.*]] = load [2 x i64], ptr [[AGG_TMP6]], align 4
+// CHECK1-NEXT: call void @_ZZNK1FIdE2akER1HENKUlS1_E_clES1_(ptr noundef nonnull align 1 dereferenceable(1) [[AP]], [2 x i64] [[TMP3]])
+// CHECK1-NEXT: ret void
+template class F<double>;
+#endif
+// CHECK-LABEL: define {{[^@]+}}@_Z5begin1gI1cE
+// CHECK-SAME: (i8 [[AC_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
+// CHECK-NEXT: [[AC:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G]], align 1
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AC]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[AC_COERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[RETVAL]], i8 [[TMP0]])
+// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
+// CHECK-NEXT: ret i8 [[TMP1]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEC1E1gIS0_E
+// CHECK-SAME: (ptr noundef nonnull returned align 1 dereferenceable(1) [[THIS:%.*]], i8 [[DOTCOERCE:%.*]]) unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC2E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i8 [[TMP1]])
+// CHECK-NEXT: ret ptr [[THIS1]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEC2E1gIS0_E
+// CHECK-SAME: (ptr noundef nonnull returned align 1 dereferenceable(1) [[THIS:%.*]], i8 [[DOTCOERCE:%.*]]) unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i32 noundef 0)
+// CHECK-NEXT: ret ptr [[THIS1]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZNK1FIdE2akER1H
+// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[AN:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[AN_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[AO:%.*]] = alloca [[CLASS_O:%.*]], align 1
+// CHECK-NEXT: [[UNDEF_AGG_TMP:%.*]] = alloca [[CLASS_O]], align 1
+// CHECK-NEXT: [[AP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// CHECK-NEXT: [[AR:%.*]] = alloca [[CLASS_H:%.*]], align 4
+// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B:%.*]], align 1
+// CHECK-NEXT: [[AGG_TMP2:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_H]], align 4
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: store ptr [[AN]], ptr [[AN_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AN_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
+// CHECK-NEXT: call void @_ZN1H1sEv(ptr noundef nonnull align 4 dereferenceable(16) [[TMP0]])
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP]], i32 noundef 0)
+// CHECK-NEXT: [[CALL3:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP2]], i32 noundef 0)
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP2]], i32 0, i32 0
+// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK-NEXT: [[CALL5:%.*]] = call noundef ptr @_ZN1HC1E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[AR]], i8 [[TMP1]], i8 [[TMP2]])
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP6]], ptr align 4 [[AR]], i64 16, i1 false)
+// CHECK-NEXT: [[TMP3:%.*]] = load [2 x i64], ptr [[AGG_TMP6]], align 4
+// CHECK-NEXT: call void @_ZZNK1FIdE2akER1HENKUlS1_E_clES1_(ptr noundef nonnull align 1 dereferenceable(1) [[AP]], [2 x i64] [[TMP3]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1H1sEv
+// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[THIS1]], i64 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1HC1E1bS0_
+// CHECK-SAME: (ptr noundef nonnull returned align 4 dereferenceable(16) [[THIS:%.*]], i8 [[AG_COERCE:%.*]], i8 [[R_COERCE:%.*]]) unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
+// CHECK-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[AG_COERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[R_COERCE]], ptr [[COERCE_DIVE1]], align 1
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[COERCE_DIVE3:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE3]], align 1
+// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1HC2E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[THIS2]], i8 [[TMP0]], i8 [[TMP1]])
+// CHECK-NEXT: ret ptr [[THIS2]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZZNK1FIdE2akER1HENKUlS1_E_clES1_
+// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]], [2 x i64] [[DOTCOERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_H:%.*]], align 4
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[TMP:%.*]] = alloca [[CLASS_I:%.*]], align 1
+// CHECK-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[__END3:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_O:%.*]], align 1
+// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[AGG_TMP3:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[AGG_TMP9:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[__BEGIN3:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[__BEGIN313:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[AGG_TMP14:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[__BEGIN318:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[D:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
+// CHECK-NEXT: store [2 x i64] [[DOTCOERCE]], ptr [[TMP0]], align 4
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: store ptr [[THIS1]], ptr [[__RANGE3]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META3]]
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_O]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call i8 @_Z3endI1oEDaT_(i8 [[TMP3]])
+// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[__END3]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[CALL]], ptr [[COERCE_DIVE2]], align 1
+// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META3]]
+// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK-NEXT: [[CALL5:%.*]] = call i8 @_Z5begin1gI1cE(i8 [[TMP5]])
+// CHECK-NEXT: [[COERCE_DIVE6:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[DOTCAPTURE_EXPR_]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[CALL5]], ptr [[COERCE_DIVE6]], align 1
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTCAPTURE_EXPR_7]], ptr align 1 [[__END3]], i64 1, i1 false)
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[AGG_TMP9]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
+// CHECK-NEXT: [[COERCE_DIVE10:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[AGG_TMP9]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[COERCE_DIVE10]], align 1
+// CHECK-NEXT: [[COERCE_VAL_II:%.*]] = zext i8 [[TMP6]] to i64
+// CHECK-NEXT: [[CALL11:%.*]] = call noundef i64 @_ZN1iI1cEmiES1_(ptr noundef nonnull align 1 dereferenceable(1) [[DOTCAPTURE_EXPR_7]], i64 [[COERCE_VAL_II]])
+// CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[CALL11]], 1
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK-NEXT: [[SUB12:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK-NEXT: store i64 [[SUB12]], ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[__BEGIN3]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[AGG_TMP14]], ptr align 1 [[__END3]], i64 1, i1 false)
+// CHECK-NEXT: [[COERCE_DIVE15:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[AGG_TMP14]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[COERCE_DIVE15]], align 1
+// CHECK-NEXT: [[COERCE_VAL_II16:%.*]] = zext i8 [[TMP7]] to i64
+// CHECK-NEXT: [[CALL17:%.*]] = call noundef i1 @_ZN1iI1cEneES1_(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN3]], i64 [[COERCE_VAL_II16]])
+// CHECK-NEXT: br i1 [[CALL17]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK: omp.precond.then:
+// CHECK-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
+// CHECK-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP9]], [[TMP10]]
+// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK: cond.true:
+// CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK-NEXT: br label [[COND_END:%.*]]
+// CHECK: cond.false:
+// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK-NEXT: br label [[COND_END]]
+// CHECK: cond.end:
+// CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
+// CHECK-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 8
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK: omp.inner.for.cond:
+// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
+// CHECK-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK: omp.inner.for.body:
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[__BEGIN318]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
+// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP16]], 1
+// CHECK-NEXT: call void @_ZN1iI1cEpLEl(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN318]], i64 noundef [[MUL]])
+// CHECK-NEXT: [[CALL20:%.*]] = call noundef i32 @_ZN1iI1cEdeEv(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN318]])
+// CHECK-NEXT: store i32 [[CALL20]], ptr [[D]], align 4
+// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK: omp.body.continue:
+// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK: omp.inner.for.inc:
+// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1
+// CHECK-NEXT: store i64 [[ADD21]], ptr [[DOTOMP_IV]], align 8
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK: omp.inner.for.end:
+// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK: omp.precond.end:
+// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1HC2E1bS0_
+// CHECK-SAME: (ptr noundef nonnull returned align 4 dereferenceable(16) [[THIS:%.*]], i8 [[AG_COERCE:%.*]], i8 [[R_COERCE:%.*]]) unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
+// CHECK-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[AGG_TMP3:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[AGG_TMP8:%.*]] = alloca [[CLASS_B]], align 1
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[AG_COERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[R_COERCE]], ptr [[COERCE_DIVE1]], align 1
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
+// CHECK-NEXT: [[COERCE_DIVE5:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE5]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1DC2Eii1bS0_1a(ptr noundef nonnull align 1 dereferenceable(1) [[THIS2]], i32 noundef 0, i32 noundef 0, i8 [[TMP0]], i8 [[TMP1]], i32 noundef 0)
+// CHECK-NEXT: [[AF:%.*]] = getelementptr inbounds nuw [[CLASS_H:%.*]], ptr [[THIS2]], i32 0, i32 0
+// CHECK-NEXT: store i32 0, ptr [[AF]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[THIS2]], i64 4
+// CHECK-NEXT: [[CALL7:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP6]], i32 noundef 0)
+// CHECK-NEXT: [[CALL9:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP8]], i32 noundef 0)
+// CHECK-NEXT: [[COERCE_DIVE10:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP6]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[COERCE_DIVE10]], align 1
+// CHECK-NEXT: [[COERCE_DIVE11:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP8]], i32 0, i32 0
+// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[COERCE_DIVE11]], align 1
+// CHECK-NEXT: [[CALL12:%.*]] = call noundef ptr @_ZN1oC1Ei1bS0_(ptr noundef nonnull align 1 dereferenceable(1) [[TMP2]], i32 noundef 0, i8 [[TMP3]], i8 [[TMP4]])
+// CHECK-NEXT: [[V:%.*]] = getelementptr inbounds nuw [[CLASS_H]], ptr [[THIS2]], i32 0, i32 2
+// CHECK-NEXT: store i32 0, ptr [[V]], align 4
+// CHECK-NEXT: [[Q:%.*]] = getelementptr inbounds nuw [[CLASS_H]], ptr [[THIS2]], i32 0, i32 3
+// CHECK-NEXT: store i32 0, ptr [[Q]], align 4
+// CHECK-NEXT: ret ptr [[THIS2]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_Z3endI1oEDaT_
+// CHECK-SAME: (i8 [[AC_COERCE:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
+// CHECK-NEXT: [[AC:%.*]] = alloca [[CLASS_O:%.*]], align 1
+// CHECK-NEXT: [[AD:%.*]] = alloca [[CLASS_I]], align 1
+// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G:%.*]], align 1
+// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_O]], ptr [[AC]], i32 0, i32 0
+// CHECK-NEXT: store i8 [[AC_COERCE]], ptr [[COERCE_DIVE]], align 1
+// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
+// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[AD]], i8 [[TMP0]])
+// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[RETVAL]], ptr align 1 [[AD]], i64 1, i1 false)
+// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
+// CHECK-NEXT: ret i8 [[TMP1]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEdeEv
+// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4
+// CHECK-NEXT: ret i32 [[TMP0]]
+//
>From 250200abec9dfb44a50813f90297c410d036533e Mon Sep 17 00:00:00 2001
From: Shivam Gupta <shivam98.tkg at gmail.com>
Date: Mon, 2 Mar 2026 13:20:41 +0530
Subject: [PATCH 2/2] Emit C++ range-for implicit variables before OpenMP loop
privatization
---
clang/lib/CodeGen/CGStmtOpenMP.cpp | 33 +-
clang/test/OpenMP/for_range_loop_codegen.cpp | 435 +---
clang/test/OpenMP/parallel_for_codegen.cpp | 2238 +++++++++---------
3 files changed, 1163 insertions(+), 1543 deletions(-)
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index 239914418cade..cc85de9221eef 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -150,6 +150,20 @@ class OMPLoopScope : public CodeGenFunction::RunCleanupsScope {
const Stmt *PreInits;
CodeGenFunction::OMPMapVars PreCondVars;
if (auto *LD = dyn_cast<OMPLoopDirective>(&S)) {
+ // Emit init, __range, __begin and __end variables for C++ range loops.
+ (void)OMPLoopBasedDirective::doForAllLoops(
+ LD->getInnermostCapturedStmt()->getCapturedStmt(),
+ /*TryImperfectlyNestedLoops=*/true, LD->getLoopsNumber(),
+ [&CGF](unsigned Cnt, const Stmt *CurStmt) {
+ if (const auto *CXXFor = dyn_cast<CXXForRangeStmt>(CurStmt)) {
+ if (const Stmt *Init = CXXFor->getInit())
+ CGF.EmitStmt(Init);
+ CGF.EmitStmt(CXXFor->getRangeStmt());
+ CGF.EmitStmt(CXXFor->getBeginStmt());
+ CGF.EmitStmt(CXXFor->getEndStmt());
+ }
+ return false;
+ });
llvm::DenseSet<const VarDecl *> EmittedAsPrivate;
for (const auto *E : LD->counters()) {
const auto *VD = cast<VarDecl>(cast<DeclRefExpr>(E)->getDecl());
@@ -174,19 +188,6 @@ class OMPLoopScope : public CodeGenFunction::RunCleanupsScope {
}
}
(void)PreCondVars.apply(CGF);
- // Emit init, __range and __end variables for C++ range loops.
- (void)OMPLoopBasedDirective::doForAllLoops(
- LD->getInnermostCapturedStmt()->getCapturedStmt(),
- /*TryImperfectlyNestedLoops=*/true, LD->getLoopsNumber(),
- [&CGF](unsigned Cnt, const Stmt *CurStmt) {
- if (const auto *CXXFor = dyn_cast<CXXForRangeStmt>(CurStmt)) {
- if (const Stmt *Init = CXXFor->getInit())
- CGF.EmitStmt(Init);
- CGF.EmitStmt(CXXFor->getRangeStmt());
- CGF.EmitStmt(CXXFor->getEndStmt());
- }
- return false;
- });
PreInits = LD->getPreInits();
} else if (const auto *Tile = dyn_cast<OMPTileDirective>(&S)) {
PreInits = Tile->getPreInits();
@@ -2395,12 +2396,6 @@ void CodeGenFunction::EmitOMPPrivateLoopCounters(
for (const Expr *E : S.counters()) {
const auto *VD = cast<VarDecl>(cast<DeclRefExpr>(E)->getDecl());
const auto *PrivateVD = cast<VarDecl>(cast<DeclRefExpr>(*I)->getDecl());
- // Privatize original counter variable (e.g., __beginN, __endN, __rangeN)
- if (!LocalDeclMap.count(VD)) {
- Address Addr = CreateMemTemp(VD->getType(), VD->getName());
- LocalDeclMap.insert({VD, Addr});
- (void)LoopScope.addPrivate(VD, Addr);
- }
// Emit var without initialization.
AutoVarEmission VarEmission = EmitAutoVarAlloca(*PrivateVD);
EmitAutoVarCleanups(VarEmission);
diff --git a/clang/test/OpenMP/for_range_loop_codegen.cpp b/clang/test/OpenMP/for_range_loop_codegen.cpp
index bc86c7a477210..44441e122d5e5 100644
--- a/clang/test/OpenMP/for_range_loop_codegen.cpp
+++ b/clang/test/OpenMP/for_range_loop_codegen.cpp
@@ -1,419 +1,32 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --clang-args ['-fopenmp', '-std=c++20'] --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
-// RUN: %clang_cc1 -verify -fopenmp -std=c++20 -emit-llvm %s -o - | FileCheck %s
-// expected-no-diagnostics
-#ifndef HEADER
-#define HEADER
+// RUN: %clang_cc1 -fopenmp -emit-llvm -std=c++20 %s -o -
+struct Iter {
+ const int *Ptr;
-enum a {};
-class b {
-public:
- b(int);
+ bool operator!=(const Iter &Other) const { return Ptr != Other.Ptr; }
+ void operator++() { ++Ptr; }
+ const int &operator*() const { return *Ptr; }
+ long operator-(const Iter &Other) const { return Ptr - Other.Ptr; }
+ void operator+=(long N) { Ptr += N; }
};
-struct c {
- typedef b h;
-};
-using e = b;
-using f = b;
-template <typename> class g {};
-template <typename l> class i {
-public:
- using j = long;
- l::h aa;
- i(g<l>) : aa{0} {}
- bool operator!=(i);
- void operator++();
- auto operator*() {
- int k;
- return k;
- }
- j operator-(i);
- void operator+=(j);
-};
-class o : public g<c> {
-public:
- using p = int;
- o(p, e, f);
-};
-// CHECK1-LABEL: @_Z5begin1gI1cE(
-// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
-// CHECK1-NEXT: [[AC:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G]], align 1
-// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AC]], i32 0, i32 0
-// CHECK1-NEXT: store i8 [[AC_COERCE:%.*]], ptr [[COERCE_DIVE]], align 1
-// CHECK1-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
-// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[RETVAL]], i8 [[TMP0]])
-// CHECK1-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
-// CHECK1-NEXT: ret i8 [[TMP1]]
-auto begin(g<c> ac) {
- i ad(ac);
- return ad;
-}
-template <typename l> auto end(l ac) {
- i ad(ac);
- return ad;
-}
-using m = b;
-using n = b;
-class D {
-protected:
- D(int, int, n, m, a);
-};
-class H : D {
- int af;
- o t;
-public:
- a v;
- int q;
-// CHECK1-LABEL: @_ZN1HC1E1bS0_(
-// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
-// CHECK1-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
-// CHECK1-NEXT: store i8 [[AG_COERCE:%.*]], ptr [[COERCE_DIVE]], align 1
-// CHECK1-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
-// CHECK1-NEXT: store i8 [[R_COERCE:%.*]], ptr [[COERCE_DIVE1]], align 1
-// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: [[COERCE_DIVE3:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE3]], align 1
-// CHECK1-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1HC2E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[THIS2]], i8 [[TMP0]], i8 [[TMP1]])
-// CHECK1-NEXT: ret ptr [[THIS2]]
- H(n ag, m r) : D(0, 0, ag, r, a{}), af(0), t{o(0, 0, 0)}, q(0), v() {}
-// CHECK1-LABEL: @_ZN1H1sEv(
-// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[THIS1]], i64 4
-// CHECK1-NEXT: ret void
- auto s() { return t; }
+struct Range {
+ int Data[4];
};
-template <typename> class F { void ak(H &) const; };
-template <typename am> void F<am>::ak(H &an) const {
- auto ao = an.s();
- auto ap = [ao](H) {
+
+Iter begin(const Range &R) { return {R.Data}; }
+Iter end(const Range &R) { return {R.Data + 4}; }
+
+template <typename T>
+void foo() {
+ Range R;
+
+ auto lambda = [R]() {
#pragma omp for
- for (auto d : ao)
+ for (auto x : R)
;
};
- H ar(0, 0);
- ap(ar);
+
+ lambda();
}
-// CHECK1-LABEL: @_ZNK1FIdE2akER1H(
-// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK1-NEXT: [[AN_ADDR:%.*]] = alloca ptr, align 8
-// CHECK1-NEXT: [[AO:%.*]] = alloca [[CLASS_O:%.*]], align 1
-// CHECK1-NEXT: [[UNDEF_AGG_TMP:%.*]] = alloca [[CLASS_O]], align 1
-// CHECK1-NEXT: [[AP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
-// CHECK1-NEXT: [[AR:%.*]] = alloca [[CLASS_H:%.*]], align 4
-// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B:%.*]], align 1
-// CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_H]], align 4
-// CHECK1-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: store ptr [[AN:%.*]], ptr [[AN_ADDR]], align 8
-// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AN_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
-// CHECK1-NEXT: call void @_ZN1H1sEv(ptr noundef nonnull align 4 dereferenceable(16) [[TMP0]])
-// CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP]], i32 noundef 0)
-// CHECK1-NEXT: [[CALL3:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP2]], i32 noundef 0)
-// CHECK1-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
-// CHECK1-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP2]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK1-NEXT: [[CALL5:%.*]] = call noundef ptr @_ZN1HC1E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[AR]], i8 [[TMP1]], i8 [[TMP2]])
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP6]], ptr align 4 [[AR]], i64 16, i1 false)
-// CHECK1-NEXT: [[TMP3:%.*]] = load [2 x i64], ptr [[AGG_TMP6]], align 4
-// CHECK1-NEXT: call void @_ZZNK1FIdE2akER1HENKUlS1_E_clES1_(ptr noundef nonnull align 1 dereferenceable(1) [[AP]], [2 x i64] [[TMP3]])
-// CHECK1-NEXT: ret void
-template class F<double>;
-#endif
-// CHECK-LABEL: define {{[^@]+}}@_Z5begin1gI1cE
-// CHECK-SAME: (i8 [[AC_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
-// CHECK-NEXT: [[AC:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G]], align 1
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AC]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[AC_COERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[RETVAL]], i8 [[TMP0]])
-// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
-// CHECK-NEXT: ret i8 [[TMP1]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEC1E1gIS0_E
-// CHECK-SAME: (ptr noundef nonnull returned align 1 dereferenceable(1) [[THIS:%.*]], i8 [[DOTCOERCE:%.*]]) unnamed_addr #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC2E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i8 [[TMP1]])
-// CHECK-NEXT: ret ptr [[THIS1]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEC2E1gIS0_E
-// CHECK-SAME: (ptr noundef nonnull returned align 1 dereferenceable(1) [[THIS:%.*]], i8 [[DOTCOERCE:%.*]]) unnamed_addr #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[TMP0]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]], i32 noundef 0)
-// CHECK-NEXT: ret ptr [[THIS1]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZNK1FIdE2akER1H
-// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[AN:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[AN_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[AO:%.*]] = alloca [[CLASS_O:%.*]], align 1
-// CHECK-NEXT: [[UNDEF_AGG_TMP:%.*]] = alloca [[CLASS_O]], align 1
-// CHECK-NEXT: [[AP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
-// CHECK-NEXT: [[AR:%.*]] = alloca [[CLASS_H:%.*]], align 4
-// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B:%.*]], align 1
-// CHECK-NEXT: [[AGG_TMP2:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_H]], align 4
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: store ptr [[AN]], ptr [[AN_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AN_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
-// CHECK-NEXT: call void @_ZN1H1sEv(ptr noundef nonnull align 4 dereferenceable(16) [[TMP0]])
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP]], i32 noundef 0)
-// CHECK-NEXT: [[CALL3:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP2]], i32 noundef 0)
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP2]], i32 0, i32 0
-// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK-NEXT: [[CALL5:%.*]] = call noundef ptr @_ZN1HC1E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[AR]], i8 [[TMP1]], i8 [[TMP2]])
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP6]], ptr align 4 [[AR]], i64 16, i1 false)
-// CHECK-NEXT: [[TMP3:%.*]] = load [2 x i64], ptr [[AGG_TMP6]], align 4
-// CHECK-NEXT: call void @_ZZNK1FIdE2akER1HENKUlS1_E_clES1_(ptr noundef nonnull align 1 dereferenceable(1) [[AP]], [2 x i64] [[TMP3]])
-// CHECK-NEXT: ret void
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1H1sEv
-// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[THIS1]], i64 4
-// CHECK-NEXT: ret void
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1HC1E1bS0_
-// CHECK-SAME: (ptr noundef nonnull returned align 4 dereferenceable(16) [[THIS:%.*]], i8 [[AG_COERCE:%.*]], i8 [[R_COERCE:%.*]]) unnamed_addr #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
-// CHECK-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[AG_COERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[R_COERCE]], ptr [[COERCE_DIVE1]], align 1
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[COERCE_DIVE3:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
-// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE3]], align 1
-// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1HC2E1bS0_(ptr noundef nonnull align 4 dereferenceable(16) [[THIS2]], i8 [[TMP0]], i8 [[TMP1]])
-// CHECK-NEXT: ret ptr [[THIS2]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZZNK1FIdE2akER1HENKUlS1_E_clES1_
-// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]], [2 x i64] [[DOTCOERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CLASS_H:%.*]], align 4
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[TMP:%.*]] = alloca [[CLASS_I:%.*]], align 1
-// CHECK-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[__END3:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_O:%.*]], align 1
-// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[AGG_TMP3:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[AGG_TMP9:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[__BEGIN3:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[__BEGIN313:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[AGG_TMP14:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-NEXT: [[__BEGIN318:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[D:%.*]] = alloca i32, align 4
-// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
-// CHECK-NEXT: store [2 x i64] [[DOTCOERCE]], ptr [[TMP0]], align 4
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: store ptr [[THIS1]], ptr [[__RANGE3]], align 8
-// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META3]]
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_O]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call i8 @_Z3endI1oEDaT_(i8 [[TMP3]])
-// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[__END3]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[CALL]], ptr [[COERCE_DIVE2]], align 1
-// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META3]]
-// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP3]], i32 0, i32 0
-// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK-NEXT: [[CALL5:%.*]] = call i8 @_Z5begin1gI1cE(i8 [[TMP5]])
-// CHECK-NEXT: [[COERCE_DIVE6:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[DOTCAPTURE_EXPR_]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[CALL5]], ptr [[COERCE_DIVE6]], align 1
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTCAPTURE_EXPR_7]], ptr align 1 [[__END3]], i64 1, i1 false)
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[AGG_TMP9]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
-// CHECK-NEXT: [[COERCE_DIVE10:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[AGG_TMP9]], i32 0, i32 0
-// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[COERCE_DIVE10]], align 1
-// CHECK-NEXT: [[COERCE_VAL_II:%.*]] = zext i8 [[TMP6]] to i64
-// CHECK-NEXT: [[CALL11:%.*]] = call noundef i64 @_ZN1iI1cEmiES1_(ptr noundef nonnull align 1 dereferenceable(1) [[DOTCAPTURE_EXPR_7]], i64 [[COERCE_VAL_II]])
-// CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[CALL11]], 1
-// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
-// CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
-// CHECK-NEXT: [[SUB12:%.*]] = sub nsw i64 [[DIV]], 1
-// CHECK-NEXT: store i64 [[SUB12]], ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[__BEGIN3]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[AGG_TMP14]], ptr align 1 [[__END3]], i64 1, i1 false)
-// CHECK-NEXT: [[COERCE_DIVE15:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[AGG_TMP14]], i32 0, i32 0
-// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[COERCE_DIVE15]], align 1
-// CHECK-NEXT: [[COERCE_VAL_II16:%.*]] = zext i8 [[TMP7]] to i64
-// CHECK-NEXT: [[CALL17:%.*]] = call noundef i1 @_ZN1iI1cEneES1_(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN3]], i64 [[COERCE_VAL_II16]])
-// CHECK-NEXT: br i1 [[CALL17]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK: omp.precond.then:
-// CHECK-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
-// CHECK-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
-// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP9]], [[TMP10]]
-// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK: cond.true:
-// CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK-NEXT: br label [[COND_END:%.*]]
-// CHECK: cond.false:
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK-NEXT: br label [[COND_END]]
-// CHECK: cond.end:
-// CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
-// CHECK-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
-// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 8
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK: omp.inner.for.cond:
-// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
-// CHECK-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK: omp.inner.for.body:
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[__BEGIN318]], ptr align 1 [[DOTCAPTURE_EXPR_]], i64 1, i1 false)
-// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP16]], 1
-// CHECK-NEXT: call void @_ZN1iI1cEpLEl(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN318]], i64 noundef [[MUL]])
-// CHECK-NEXT: [[CALL20:%.*]] = call noundef i32 @_ZN1iI1cEdeEv(ptr noundef nonnull align 1 dereferenceable(1) [[__BEGIN318]])
-// CHECK-NEXT: store i32 [[CALL20]], ptr [[D]], align 4
-// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK: omp.body.continue:
-// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK: omp.inner.for.inc:
-// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK-NEXT: [[ADD21:%.*]] = add nsw i64 [[TMP17]], 1
-// CHECK-NEXT: store i64 [[ADD21]], ptr [[DOTOMP_IV]], align 8
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK: omp.inner.for.end:
-// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK: omp.loop.exit:
-// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK: omp.precond.end:
-// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP1]])
-// CHECK-NEXT: ret void
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1HC2E1bS0_
-// CHECK-SAME: (ptr noundef nonnull returned align 4 dereferenceable(16) [[THIS:%.*]], i8 [[AG_COERCE:%.*]], i8 [[R_COERCE:%.*]]) unnamed_addr #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[AG:%.*]] = alloca [[CLASS_B:%.*]], align 1
-// CHECK-NEXT: [[R:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[AGG_TMP3:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[AGG_TMP6:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[AGG_TMP8:%.*]] = alloca [[CLASS_B]], align 1
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AG]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[AG_COERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[R]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[R_COERCE]], ptr [[COERCE_DIVE1]], align 1
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS2:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[COERCE_DIVE4:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE4]], align 1
-// CHECK-NEXT: [[COERCE_DIVE5:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP3]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE5]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1DC2Eii1bS0_1a(ptr noundef nonnull align 1 dereferenceable(1) [[THIS2]], i32 noundef 0, i32 noundef 0, i8 [[TMP0]], i8 [[TMP1]], i32 noundef 0)
-// CHECK-NEXT: [[AF:%.*]] = getelementptr inbounds nuw [[CLASS_H:%.*]], ptr [[THIS2]], i32 0, i32 0
-// CHECK-NEXT: store i32 0, ptr [[AF]], align 4
-// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[THIS2]], i64 4
-// CHECK-NEXT: [[CALL7:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP6]], i32 noundef 0)
-// CHECK-NEXT: [[CALL9:%.*]] = call noundef ptr @_ZN1bC1Ei(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP8]], i32 noundef 0)
-// CHECK-NEXT: [[COERCE_DIVE10:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP6]], i32 0, i32 0
-// CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[COERCE_DIVE10]], align 1
-// CHECK-NEXT: [[COERCE_DIVE11:%.*]] = getelementptr inbounds nuw [[CLASS_B]], ptr [[AGG_TMP8]], i32 0, i32 0
-// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[COERCE_DIVE11]], align 1
-// CHECK-NEXT: [[CALL12:%.*]] = call noundef ptr @_ZN1oC1Ei1bS0_(ptr noundef nonnull align 1 dereferenceable(1) [[TMP2]], i32 noundef 0, i8 [[TMP3]], i8 [[TMP4]])
-// CHECK-NEXT: [[V:%.*]] = getelementptr inbounds nuw [[CLASS_H]], ptr [[THIS2]], i32 0, i32 2
-// CHECK-NEXT: store i32 0, ptr [[V]], align 4
-// CHECK-NEXT: [[Q:%.*]] = getelementptr inbounds nuw [[CLASS_H]], ptr [[THIS2]], i32 0, i32 3
-// CHECK-NEXT: store i32 0, ptr [[Q]], align 4
-// CHECK-NEXT: ret ptr [[THIS2]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_Z3endI1oEDaT_
-// CHECK-SAME: (i8 [[AC_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[RETVAL:%.*]] = alloca [[CLASS_I:%.*]], align 1
-// CHECK-NEXT: [[AC:%.*]] = alloca [[CLASS_O:%.*]], align 1
-// CHECK-NEXT: [[AD:%.*]] = alloca [[CLASS_I]], align 1
-// CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_G:%.*]], align 1
-// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[CLASS_O]], ptr [[AC]], i32 0, i32 0
-// CHECK-NEXT: store i8 [[AC_COERCE]], ptr [[COERCE_DIVE]], align 1
-// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[CLASS_G]], ptr [[AGG_TMP]], i32 0, i32 0
-// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[COERCE_DIVE1]], align 1
-// CHECK-NEXT: [[CALL:%.*]] = call noundef ptr @_ZN1iI1cEC1E1gIS0_E(ptr noundef nonnull align 1 dereferenceable(1) [[AD]], i8 [[TMP0]])
-// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[RETVAL]], ptr align 1 [[AD]], i64 1, i1 false)
-// CHECK-NEXT: [[COERCE_DIVE2:%.*]] = getelementptr inbounds nuw [[CLASS_I]], ptr [[RETVAL]], i32 0, i32 0
-// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[COERCE_DIVE2]], align 1
-// CHECK-NEXT: ret i8 [[TMP1]]
-//
-//
-// CHECK-LABEL: define {{[^@]+}}@_ZN1iI1cEdeEv
-// CHECK-SAME: (ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4
-// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
-// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[K]], align 4
-// CHECK-NEXT: ret i32 [[TMP0]]
-//
+
+template void foo<int>();
diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp
index c7afae419509b..f52025aa3405f 100644
--- a/clang/test/OpenMP/parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_codegen.cpp
@@ -402,10 +402,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -511,10 +511,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -620,10 +620,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -746,10 +746,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -767,42 +767,42 @@ void range_for_collapsed() {
// CHECK1-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7:![0-9]+]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -849,10 +849,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -870,42 +870,42 @@ void range_for_collapsed() {
// CHECK1-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -964,11 +964,11 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META5]], !align [[META13:![0-9]+]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
// CHECK1-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
@@ -1010,58 +1010,58 @@ void range_for_collapsed() {
// CHECK1-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14:![0-9]+]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
-// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
// CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
-// CHECK1-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
// CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
// CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
-// CHECK1-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
-// CHECK1-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
// CHECK1-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
-// CHECK1-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
-// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
// CHECK1-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
-// CHECK1-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
-// CHECK1-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -1116,10 +1116,10 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1137,55 +1137,55 @@ void range_for_collapsed() {
// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
-// CHECK1-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
-// CHECK1-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]
-// CHECK1-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK1-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -1249,7 +1249,7 @@ void range_for_collapsed() {
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
@@ -1518,10 +1518,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1627,10 +1627,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1736,10 +1736,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1862,10 +1862,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK2-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -1883,42 +1883,42 @@ void range_for_collapsed() {
// CHECK2-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7:![0-9]+]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK2: omp.dispatch.inc:
@@ -1965,10 +1965,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK2-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -1986,42 +1986,42 @@ void range_for_collapsed() {
// CHECK2-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK2: omp.dispatch.inc:
@@ -2080,11 +2080,11 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META5]], !align [[META13:![0-9]+]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
// CHECK2-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
@@ -2126,58 +2126,58 @@ void range_for_collapsed() {
// CHECK2-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14:![0-9]+]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
-// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
// CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
-// CHECK2-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
// CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
// CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
-// CHECK2-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
-// CHECK2-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
-// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
// CHECK2-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
-// CHECK2-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
-// CHECK2-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
// CHECK2-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
-// CHECK2-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
-// CHECK2-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK2-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK2: omp.dispatch.inc:
@@ -2232,10 +2232,10 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -2253,55 +2253,55 @@ void range_for_collapsed() {
// CHECK2-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
-// CHECK2-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
-// CHECK2-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
-// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
// CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]
-// CHECK2-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
-// CHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]
-// CHECK2-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK2-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK2-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK2: omp.dispatch.inc:
@@ -2365,7 +2365,7 @@ void range_for_collapsed() {
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
@@ -2634,80 +2634,80 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG25]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG25]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG25]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]]
-// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]], !nonnull [[META9:![0-9]+]], !align [[META26:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG25]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG25]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG25]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG27:![0-9]+]]
+// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG27]]
// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]]
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG25]]
// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG26]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG26]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG27]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG27]]
// CHECK5: cond.true:
-// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG26]]
+// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG27]]
// CHECK5: cond.false:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG26]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG27]]
// CHECK5: cond.end:
-// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
+// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG27]]
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG26]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG27]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG25]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG26]]
-// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG27:![0-9]+]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG27]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG27]]
-// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG27]]
-// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG27]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG27]]
-// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG27]]
-// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG27]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG27]]
+// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG28:![0-9]+]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG28]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG28]]
+// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG28]]
+// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG28]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG28]]
+// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG28]]
+// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG28]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG29:![0-9]+]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG26]]
-// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG27]]
+// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG27]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP30:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]]
// CHECK5: omp.loop.exit:
// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG25]]
-// CHECK5-NEXT: ret void, !dbg [[DBG28]]
+// CHECK5-NEXT: ret void, !dbg [[DBG29]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG31:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -2717,12 +2717,12 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG31:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG32:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG32:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG33:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG34:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -2743,80 +2743,80 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG34]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG34]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG34]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]]
-// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG34]]
-// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG35]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG35]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG35:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG35]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG35]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG35]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG36:![0-9]+]]
+// CHECK5-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG35]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG35]]
+// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG35]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG36]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG36]]
// CHECK5: cond.true:
-// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG35]]
+// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG36]]
// CHECK5: cond.false:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG35]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG36]]
// CHECK5: cond.end:
-// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]]
+// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG35]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG35]]
-// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG34]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG36]]
+// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG35]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG35]]
-// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG36:![0-9]+]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG36]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG36]]
-// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG36]]
-// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG36]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG36]]
-// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG36]]
-// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG36]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG36]]
+// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG37:![0-9]+]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG37]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG37]]
+// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG37]]
+// CHECK5-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG37]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG38:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG35]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG35]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG36]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG36]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG35]], !llvm.loop [[LOOP39:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]]
+// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG35]]
// CHECK5: omp.loop.exit:
-// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG34]]
-// CHECK5-NEXT: ret void, !dbg [[DBG37]]
+// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG35]]
+// CHECK5-NEXT: ret void, !dbg [[DBG38]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG40:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -2826,12 +2826,12 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB19:[0-9]+]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG40:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG41:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB19:[0-9]+]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG41:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG42:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG43:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -2852,97 +2852,97 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG43:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG43]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG43]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG43]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]]
-// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG43]]
-// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG44:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG44]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG44]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG44]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45:![0-9]+]]
+// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG44]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG44]]
+// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG44]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG44]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG44]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG44]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG45]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG45]]
// CHECK5: cond.true:
-// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG44]]
+// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG45]]
// CHECK5: cond.false:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG44]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG45]]
// CHECK5: cond.end:
-// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG44]]
-// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG45]]
+// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG44]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG44]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG44]]
-// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG45]]
+// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG44]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG44]]
-// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG45:![0-9]+]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG45]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG45]]
-// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG45]]
-// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG45]]
-// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG45]]
-// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG45]]
-// CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !dbg [[DBG45]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG45]]
+// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG46:![0-9]+]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG46]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG46]]
+// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG46]]
+// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG46]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG46]]
+// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG46]]
+// CHECK5-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !dbg [[DBG46]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG47:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG44]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]]
+// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG44]], !llvm.loop [[LOOP48:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG44]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG44]]
-// CHECK5-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]]
+// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG45]]
+// CHECK5-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG45]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG44]], !llvm.loop [[LOOP49:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG43]]
-// CHECK5-NEXT: ret void, !dbg [[DBG46]]
+// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG44]]
+// CHECK5-NEXT: ret void, !dbg [[DBG47]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG50:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -2952,12 +2952,12 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB21:[0-9]+]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG50:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG51:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB21:[0-9]+]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG51:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG52:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG53:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -2978,74 +2978,74 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG53]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG53]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG53]]
-// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]]
-// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]]
-// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG53]]
-// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG54:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG54]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG54]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG54]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG55:![0-9]+]]
+// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG55]]
+// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG55]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG55]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG54]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG54]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG54]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG54]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB21]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG53]]
-// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG53]]
-// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB21]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG54]]
+// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG54]]
+// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG54]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54]]
-// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG55]]
+// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG55]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG54]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55:![0-9]+]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG54]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG54]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG55]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG55]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG54]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG54]]
-// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]]
-// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG56]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG56]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG56]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG56]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG56]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG56]]
-// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG55]]
+// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG55]]
+// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG57:![0-9]+]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG57]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG57]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG57]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG57]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG57]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG57]]
+// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG57]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG58:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG54]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG54]]
-// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG55]]
+// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG55]], !llvm.access.group [[ACC_GRP56]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG54]], !llvm.loop [[LOOP59:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG54]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG54]], !llvm.loop [[LOOP61:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB21]], i32 [[TMP5]]), !dbg [[DBG53]]
-// CHECK5-NEXT: ret void, !dbg [[DBG57]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB21]], i32 [[TMP5]]), !dbg [[DBG54]]
+// CHECK5-NEXT: ret void, !dbg [[DBG58]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG62:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -3055,12 +3055,12 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB23:[0-9]+]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG62:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB23:[0-9]+]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG63:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG64:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG65:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3081,74 +3081,74 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG65:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG65]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG65]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG65]]
-// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]]
-// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]]
-// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG65]]
-// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG66:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG66]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG66]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG66]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG67:![0-9]+]]
+// CHECK5-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG67]]
+// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG67]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG67]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG66]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG66]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(ptr @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG66]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG66]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB23]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG65]]
-// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG65]]
-// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB23]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG66]]
+// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG66]]
+// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG66]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66]]
-// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG67]]
+// CHECK5-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG67]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG66]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67:![0-9]+]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG66]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG66]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG67]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG67]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG66]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG66]]
-// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]]
-// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG68]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG68]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG68]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG68]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG68]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG68]]
-// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG67]]
+// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG67]]
+// CHECK5-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG69:![0-9]+]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG69]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG69]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG69]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG69]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG69]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG69]]
+// CHECK5-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG69]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG70:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG66]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG66]]
-// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG67]]
+// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG67]], !llvm.access.group [[ACC_GRP68]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG66]], !llvm.loop [[LOOP71:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG66]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG66]], !llvm.loop [[LOOP73:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB23]], i32 [[TMP5]]), !dbg [[DBG65]]
-// CHECK5-NEXT: ret void, !dbg [[DBG69]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB23]], i32 [[TMP5]]), !dbg [[DBG66]]
+// CHECK5-NEXT: ret void, !dbg [[DBG70]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG74:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -3160,14 +3160,14 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG74:![0-9]+]]
-// CHECK5-NEXT: store i32 0, ptr [[Y]], align 4, !dbg [[DBG75:![0-9]+]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB25:[0-9]+]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG76:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG77:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG75:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[Y]], align 4, !dbg [[DBG76:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB25:[0-9]+]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG77:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG78:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG79:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3196,119 +3196,119 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !dbg [[DBG79:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG80:![0-9]+]]
-// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG80]]
-// CHECK5-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG80]]
-// CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]]
-// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]]
-// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]]
-// CHECK5-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
-// CHECK5-NEXT: store i8 [[TMP7]], ptr [[I]], align 1, !dbg [[DBG80]]
-// CHECK5-NEXT: store i32 11, ptr [[X]], align 4, !dbg [[DBG81]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG80]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !dbg [[DBG80:![0-9]+]], !nonnull [[META9]], !align [[META81:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG80]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG80]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG80]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG80]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG82:![0-9]+]]
+// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG82]]
+// CHECK5-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG82]]
+// CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG82]]
+// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG82]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG83:![0-9]+]]
+// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG83]]
+// CHECK5-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG82]]
+// CHECK5-NEXT: store i8 [[TMP7]], ptr [[I]], align 1, !dbg [[DBG82]]
+// CHECK5-NEXT: store i32 11, ptr [[X]], align 4, !dbg [[DBG83]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG82]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG82]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG80]]
// CHECK5: omp.precond.then:
-// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
-// CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4, !dbg [[DBG79]]
-// CHECK5-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG79]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG83]]
+// CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG82]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG83]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG80]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4, !dbg [[DBG80]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_init_8(ptr @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG80]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG80]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB25]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG79]]
-// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG79]]
-// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG80]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG80]]
+// CHECK5-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB25]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG80]]
+// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG80]]
+// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG80]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG80]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82:![0-9]+]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG80]]
-// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84:![0-9]+]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG82]]
+// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG80]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG80]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG80]]
-// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]]
-// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]]
-// CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]]
-// CHECK5-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG80]]
-// CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]]
-// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG80]]
-// CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]]
-// CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]]
-// CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]]
-// CHECK5-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG83]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG83]]
-// CHECK5-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG83]]
-// CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG83]]
-// CHECK5-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG83]]
-// CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]]
-// CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG83]]
-// CHECK5-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG83]]
-// CHECK5-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]]
-// CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG83]]
-// CHECK5-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG82]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG82]]
+// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG82]]
+// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG82]]
+// CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG82]]
+// CHECK5-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG82]]
+// CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG82]]
+// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG82]]
+// CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG83]]
+// CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG83]]
+// CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG83]]
+// CHECK5-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG85:![0-9]+]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG85]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG85]]
+// CHECK5-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG85]]
+// CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG85]]
+// CHECK5-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG85]]
+// CHECK5-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG85]]
+// CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG85]]
+// CHECK5-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG85]]
+// CHECK5-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG85]]
+// CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG85]]
+// CHECK5-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !dbg [[DBG85]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG86:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG80]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG80]]
-// CHECK5-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]]
+// CHECK5-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG82]]
+// CHECK5-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG82]], !llvm.access.group [[ACC_GRP84]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG80]], !llvm.loop [[LOOP87:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG80]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG80]], !llvm.loop [[LOOP89:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
-// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4, !dbg [[DBG79]]
-// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB25]], i32 [[TMP36]]), !dbg [[DBG79]]
-// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG79]]
+// CHECK5-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG80]]
+// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4, !dbg [[DBG80]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB25]], i32 [[TMP36]]), !dbg [[DBG80]]
+// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG80]]
// CHECK5: omp.precond.end:
-// CHECK5-NEXT: ret void, !dbg [[DBG84]]
+// CHECK5-NEXT: ret void, !dbg [[DBG86]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
-// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG90:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -3319,13 +3319,13 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG89:![0-9]+]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB27:[0-9]+]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG90:![0-9]+]]
-// CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]]
+// CHECK5-NEXT: store i32 0, ptr [[X]], align 4, !dbg [[DBG91:![0-9]+]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB27:[0-9]+]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG92:![0-9]+]]
+// CHECK5-NEXT: ret void, !dbg [[DBG93:![0-9]+]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG94:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3348,94 +3348,94 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG93:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]]
-// CHECK5-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG93]]
-// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG95:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG95]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG95]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG95]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG96:![0-9]+]]
+// CHECK5-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG96]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG96]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG96]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG95]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG95]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG95]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG95]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB27]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG93]]
-// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG93]]
-// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB27]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG95]]
+// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG95]]
+// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG95]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94]]
-// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG96]]
+// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG95]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95:![0-9]+]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG94]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97:![0-9]+]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG96]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG95]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG94]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]]
-// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]]
-// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]]
-// CHECK5-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG94]]
-// CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]]
-// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG94]]
-// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]]
-// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]]
-// CHECK5-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG97]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG97]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG97]]
-// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG97]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG97]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG97]]
-// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG97]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG97]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG97]]
-// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG97]]
-// CHECK5-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG96]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG96]]
+// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG96]]
+// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG96]]
+// CHECK5-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG96]]
+// CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG96]]
+// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG96]]
+// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG98:![0-9]+]]
+// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG98]]
+// CHECK5-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !dbg [[DBG98]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG99:![0-9]+]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG99]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG99]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG99]]
+// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG99]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG99]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG99]]
+// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG99]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG99]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG99]]
+// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG99]]
+// CHECK5-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !dbg [[DBG99]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG100:![0-9]+]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG95]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG94]]
-// CHECK5-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG96]]
+// CHECK5-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP97]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP101:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG95]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG95]], !llvm.loop [[LOOP103:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB27]], i32 [[TMP5]]), !dbg [[DBG93]]
-// CHECK5-NEXT: ret void, !dbg [[DBG98]]
+// CHECK5-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB27]], i32 [[TMP5]]), !dbg [[DBG95]]
+// CHECK5-NEXT: ret void, !dbg [[DBG100]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z3foov
-// CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] {
+// CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG104:![0-9]+]] {
// CHECK5-NEXT: entry:
-// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]]
-// CHECK5-NEXT: ret i32 0, !dbg [[DBG103]]
+// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG105:![0-9]+]]
+// CHECK5-NEXT: ret i32 0, !dbg [[DBG105]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
-// CHECK5-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] {
+// CHECK5-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG106:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
@@ -3444,23 +3444,23 @@ void range_for_collapsed() {
// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
-// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]]
-// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG105]]
-// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG105]]
-// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]]
-// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG105]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
-// CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG106]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG106]]
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]]
-// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]]
-// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]]), !dbg [[DBG107]]
-// CHECK5-NEXT: ret void, !dbg [[DBG107]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG107:![0-9]+]]
+// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG107]]
+// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG107]]
+// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG107]]
+// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG107]]
+// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG107]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG108:![0-9]+]]
+// CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG108]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG108]]
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG108]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109:![0-9]+]]
+// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]]), !dbg [[DBG109]]
+// CHECK5-NEXT: ret void, !dbg [[DBG109]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
-// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG108:![0-9]+]] {
+// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG110:![0-9]+]] {
// CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -3481,104 +3481,104 @@ void range_for_collapsed() {
// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]]
-// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG109]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]]
-// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG109]]
-// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
-// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]]
-// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG109]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]]
-// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG109]]
-// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG111:![0-9]+]], !nonnull [[META9]], !align [[META26]]
+// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG112:![0-9]+]]
+// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG111]]
+// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG111]]
+// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG111]]
+// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG111]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG111]]
// CHECK5: omp.dispatch.cond:
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG110]]
-// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG110]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG112]]
+// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG112]]
// CHECK5: cond.true:
-// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG110]]
+// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG112]]
// CHECK5: cond.false:
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG110]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG112]]
// CHECK5: cond.end:
-// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG110]]
-// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG112]]
+// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG111]]
// CHECK5: omp.dispatch.cleanup:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG111]]
// CHECK5: omp.dispatch.body:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG111]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG110]]
-// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG112]]
+// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG111]]
// CHECK5: omp.inner.for.cond.cleanup:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG111]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]]
-// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG110]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG112]]
+// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG112]]
// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov()
-// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]]
+// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG113:![0-9]+]]
// CHECK5: invoke.cont:
-// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]]
-// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]], !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]
-// CHECK5-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]], !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]]
-// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]], !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]], !dbg [[DBG111]]
-// CHECK5-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]
-// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG111]]
+// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG113]]
+// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]], !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG113]]
+// CHECK5-NEXT: [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]], !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG113]]
+// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM7]], !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]], !dbg [[DBG113]]
+// CHECK5-NEXT: store float [[ADD9]], ptr [[ARRAYIDX8]], align 4, !dbg [[DBG113]]
+// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG113]]
// CHECK5: omp.body.continue:
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG111]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP112:![0-9]+]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG111]], !llvm.loop [[LOOP114:![0-9]+]]
// CHECK5: omp.inner.for.end:
-// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG109]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG111]]
// CHECK5: omp.dispatch.inc:
-// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]]
-// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
-// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG112]]
+// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG112]]
+// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG111]], !llvm.loop [[LOOP115:![0-9]+]]
// CHECK5: omp.dispatch.end:
-// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]]
-// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
-// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]]), !dbg [[DBG109]]
-// CHECK5-NEXT: ret void, !dbg [[DBG111]]
+// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG111]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG111]]
+// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]]), !dbg [[DBG111]]
+// CHECK5-NEXT: ret void, !dbg [[DBG113]]
// CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }
-// CHECK5-NEXT: catch ptr null, !dbg [[DBG111]]
-// CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG111]]
-// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]]
-// CHECK5-NEXT: unreachable, !dbg [[DBG111]]
+// CHECK5-NEXT: catch ptr null, !dbg [[DBG113]]
+// CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG113]]
+// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG113]]
+// CHECK5-NEXT: unreachable, !dbg [[DBG113]]
//
//
// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
@@ -3750,10 +3750,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3859,10 +3859,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3968,10 +3968,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -4094,10 +4094,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK6-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -4115,42 +4115,42 @@ void range_for_collapsed() {
// CHECK6-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond:
-// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
-// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7:![0-9]+]]
+// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc:
-// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
+// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
-// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP7]]
+// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK6: omp.dispatch.inc:
@@ -4197,10 +4197,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK6-NEXT: store i64 16908287, ptr [[DOTOMP_UB]], align 8
// CHECK6-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -4218,42 +4218,42 @@ void range_for_collapsed() {
// CHECK6-NEXT: store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond:
-// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
-// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]]
+// CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
-// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP11]], i64 [[TMP12]]
-// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP14]], i64 [[TMP15]]
-// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
-// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP17]], i64 [[TMP18]]
-// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
-// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP20]], i64 [[TMP21]]
-// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc:
-// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
+// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
-// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
-// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK6-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP10]]
+// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
// CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK6: omp.dispatch.inc:
@@ -4312,11 +4312,11 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !nonnull [[META5]], !align [[META13:![0-9]+]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
// CHECK6-NEXT: store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
@@ -4358,58 +4358,58 @@ void range_for_collapsed() {
// CHECK6-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond:
-// CHECK6-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
-// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14:![0-9]+]]
+// CHECK6-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
-// CHECK6-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
// CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
// CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
-// CHECK6-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
// CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
// CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
// CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
// CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
-// CHECK6-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
-// CHECK6-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
// CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
-// CHECK6-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
-// CHECK6-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
// CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
-// CHECK6-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
-// CHECK6-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
// CHECK6-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
-// CHECK6-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc:
-// CHECK6-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
+// CHECK6-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
-// CHECK6-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
-// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK6-NEXT: store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
// CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK6: omp.dispatch.inc:
@@ -4464,10 +4464,10 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK6-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK6-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
-// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
-// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
-// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
+// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 199, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -4485,55 +4485,55 @@ void range_for_collapsed() {
// CHECK6-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK6: omp.inner.for.cond:
-// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
-// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
+// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK6: omp.inner.for.body:
-// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
-// CHECK6-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
// CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
-// CHECK6-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK6-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
// CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds nuw float, ptr [[TMP16]], i64 [[IDXPROM6]]
-// CHECK6-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
-// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
// CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw float, ptr [[TMP19]], i64 [[IDXPROM9]]
-// CHECK6-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
-// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw float, ptr [[TMP22]], i64 [[IDXPROM12]]
-// CHECK6-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK6: omp.body.continue:
// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK6: omp.inner.for.inc:
-// CHECK6-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
+// CHECK6-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK6-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
-// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK6-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK6: omp.inner.for.end:
// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK6: omp.dispatch.inc:
@@ -4597,7 +4597,7 @@ void range_for_collapsed() {
// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK6-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
-// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]]
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
@@ -4816,103 +4816,107 @@ void range_for_collapsed() {
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
-// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__END1:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
-// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
+// CHECK11-NEXT: [[__BEGIN16:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN17:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR]], align 8
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]]
// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE1]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0
-// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 10
-// CHECK11-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 8
-// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8
+// CHECK11-NEXT: store ptr [[ARRAYDECAY]], ptr [[__BEGIN1]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
// CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 0
-// CHECK11-NEXT: store ptr [[ARRAYDECAY1]], ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END1]], align 8
-// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
-// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 8
-// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY1]], i64 10
+// CHECK11-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 8
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP3]], i64 0, i64 0
+// CHECK11-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END1]], align 8
+// CHECK11-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i64
// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
-// CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1
-// CHECK11-NEXT: store i64 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 8
-// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: store ptr [[TMP6]], ptr [[__BEGIN1]], align 8
+// CHECK11-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK11-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 8
-// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP7]], [[TMP8]]
+// CHECK11-NEXT: store ptr [[TMP7]], ptr [[__BEGIN16]], align 8
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP8]], [[TMP9]]
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK11: omp.precond.then:
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
-// CHECK11-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
-// CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
-// CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP12]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK11-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK11-NEXT: [[CMP8:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]]
+// CHECK11-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK11: cond.true:
-// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
// CHECK11-NEXT: br label [[COND_END:%.*]]
// CHECK11: cond.false:
-// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK11-NEXT: br label [[COND_END]]
// CHECK11: cond.end:
-// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
+// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ]
// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK11-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK11-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV]], align 8
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK11: omp.inner.for.cond:
-// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
-// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP18]], [[TMP19]]
+// CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body:
-// CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1
-// CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[MUL]]
-// CHECK11-NEXT: store ptr [[ADD_PTR8]], ptr [[__BEGIN15]], align 8
-// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[__BEGIN15]], align 8
-// CHECK11-NEXT: store ptr [[TMP21]], ptr [[A]], align 8
-// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[A]], align 8
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP21]], 1
+// CHECK11-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds i32, ptr [[TMP20]], i64 [[MUL]]
+// CHECK11-NEXT: store ptr [[ADD_PTR10]], ptr [[__BEGIN17]], align 8
+// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[__BEGIN17]], align 8
+// CHECK11-NEXT: store ptr [[TMP22]], ptr [[A]], align 8
+// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]]
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc:
-// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1
-// CHECK11-NEXT: store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i64 [[TMP24]], 1
+// CHECK11-NEXT: store i64 [[ADD11]], ptr [[DOTOMP_IV]], align 8
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK11: omp.inner.for.end:
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK11: omp.loop.exit:
-// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
-// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])
+// CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
+// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
// CHECK11: omp.precond.end:
// CHECK11-NEXT: ret void
@@ -4934,183 +4938,191 @@ void range_for_collapsed() {
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
-// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__RANGE1:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__END1:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[__END2:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8
-// CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i64, align 8
+// CHECK11-NEXT: [[__BEGIN120:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN221:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN123:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[__BEGIN224:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK11-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR]], align 8
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]]
// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE1]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0
-// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 10
+// CHECK11-NEXT: store ptr [[ARRAYDECAY]], ptr [[__BEGIN1]], align 8
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 0
+// CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY1]], i64 10
// CHECK11-NEXT: store ptr [[ADD_PTR]], ptr [[__END1]], align 8
// CHECK11-NEXT: store ptr [[TMP0]], ptr [[__RANGE2]], align 8
-// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
-// CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 0
-// CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY2]], i64 10
-// CHECK11-NEXT: store ptr [[ADD_PTR3]], ptr [[__END2]], align 8
-// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE1]], align 8
-// CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP3]], i64 0, i64 0
-// CHECK11-NEXT: store ptr [[ARRAYDECAY4]], ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END1]], align 8
-// CHECK11-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[__RANGE2]], align 8
-// CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP5]], i64 0, i64 0
-// CHECK11-NEXT: store ptr [[ARRAYDECAY7]], ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[__END2]], align 8
-// CHECK11-NEXT: store ptr [[TMP6]], ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP7]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP8]] to i64
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP3]], i64 0, i64 0
+// CHECK11-NEXT: store ptr [[ARRAYDECAY2]], ptr [[__BEGIN2]], align 8
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], i64 0, i64 0
+// CHECK11-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY3]], i64 10
+// CHECK11-NEXT: store ptr [[ADD_PTR4]], ptr [[__END2]], align 8
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[__RANGE1]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY6:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP5]], i64 0, i64 0
+// CHECK11-NEXT: store ptr [[ARRAYDECAY6]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[__END1]], align 8
+// CHECK11-NEXT: store ptr [[TMP6]], ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP7]], i64 0, i64 0
+// CHECK11-NEXT: store ptr [[ARRAYDECAY9]], ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__END2]], align 8
+// CHECK11-NEXT: store ptr [[TMP8]], ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP9]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP10]] to i64
// CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
// CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
-// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint ptr [[TMP9]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint ptr [[TMP10]] to i64
-// CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]]
-// CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4
-// CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1
-// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1
-// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1
-// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]]
-// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1
-// CHECK11-NEXT: store i64 [[SUB17]], ptr [[DOTCAPTURE_EXPR_9]], align 8
-// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: store ptr [[TMP11]], ptr [[__BEGIN1]], align 8
-// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: store ptr [[TMP12]], ptr [[__BEGIN2]], align 8
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST12:%.*]] = ptrtoint ptr [[TMP11]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST13:%.*]] = ptrtoint ptr [[TMP12]] to i64
+// CHECK11-NEXT: [[SUB_PTR_SUB14:%.*]] = sub i64 [[SUB_PTR_LHS_CAST12]], [[SUB_PTR_RHS_CAST13]]
+// CHECK11-NEXT: [[SUB_PTR_DIV15:%.*]] = sdiv exact i64 [[SUB_PTR_SUB14]], 4
+// CHECK11-NEXT: [[SUB16:%.*]] = sub nsw i64 [[SUB_PTR_DIV15]], 1
+// CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[SUB16]], 1
+// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i64 [[ADD17]], 1
+// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV18]]
+// CHECK11-NEXT: [[SUB19:%.*]] = sub nsw i64 [[MUL]], 1
+// CHECK11-NEXT: store i64 [[SUB19]], ptr [[DOTCAPTURE_EXPR_11]], align 8
// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 8
-// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP13]], [[TMP14]]
+// CHECK11-NEXT: store ptr [[TMP13]], ptr [[__BEGIN120]], align 8
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: store ptr [[TMP14]], ptr [[__BEGIN221]], align 8
+// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK11-NEXT: [[CMP:%.*]] = icmp ult ptr [[TMP15]], [[TMP16]]
// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
// CHECK11: land.lhs.true:
-// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[CMP18:%.*]] = icmp ult ptr [[TMP15]], [[TMP16]]
-// CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[CMP22:%.*]] = icmp ult ptr [[TMP17]], [[TMP18]]
+// CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
// CHECK11: omp.precond.then:
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
-// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
-// CHECK11-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_11]], align 8
+// CHECK11-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP19]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
-// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
-// CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]
-// CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP21]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_11]], align 8
+// CHECK11-NEXT: [[CMP25:%.*]] = icmp sgt i64 [[TMP22]], [[TMP23]]
+// CHECK11-NEXT: br i1 [[CMP25]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK11: cond.true:
-// CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
+// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_11]], align 8
// CHECK11-NEXT: br label [[COND_END:%.*]]
// CHECK11: cond.false:
-// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK11-NEXT: br label [[COND_END]]
// CHECK11: cond.end:
-// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]
+// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP24]], [[COND_TRUE]] ], [ [[TMP25]], [[COND_FALSE]] ]
// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
-// CHECK11-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK11-NEXT: store i64 [[TMP26]], ptr [[DOTOMP_IV]], align 8
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK11: omp.inner.for.cond:
-// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
-// CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]
-// CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK11-NEXT: [[CMP26:%.*]] = icmp sle i64 [[TMP27]], [[TMP28]]
+// CHECK11-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK11: omp.inner.for.body:
-// CHECK11-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
-// CHECK11-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint ptr [[TMP29]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint ptr [[TMP30]] to i64
-// CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]]
-// CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4
-// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1
-// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1
-// CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1
-// CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]]
-// CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]]
-// CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1
-// CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i64 [[MUL32]]
-// CHECK11-NEXT: store ptr [[ADD_PTR33]], ptr [[__BEGIN119]], align 8
-// CHECK11-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint ptr [[TMP34]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint ptr [[TMP35]] to i64
-// CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]]
-// CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4
-// CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1
-// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1
-// CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1
-// CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]]
-// CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]]
-// CHECK11-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
-// CHECK11-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
-// CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint ptr [[TMP36]] to i64
-// CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint ptr [[TMP37]] to i64
-// CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]]
-// CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4
-// CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1
-// CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1
-// CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1
-// CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]]
-// CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]]
-// CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]]
-// CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1
-// CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, ptr [[TMP31]], i64 [[MUL53]]
-// CHECK11-NEXT: store ptr [[ADD_PTR54]], ptr [[__BEGIN220]], align 8
-// CHECK11-NEXT: [[TMP38:%.*]] = load ptr, ptr [[__BEGIN119]], align 8
-// CHECK11-NEXT: store ptr [[TMP38]], ptr [[A]], align 8
-// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[__BEGIN220]], align 8
-// CHECK11-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
-// CHECK11-NEXT: store i32 [[TMP40]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A]], align 8
-// CHECK11-NEXT: store i32 [[TMP41]], ptr [[TMP42]], align 4
+// CHECK11-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST27:%.*]] = ptrtoint ptr [[TMP31]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST28:%.*]] = ptrtoint ptr [[TMP32]] to i64
+// CHECK11-NEXT: [[SUB_PTR_SUB29:%.*]] = sub i64 [[SUB_PTR_LHS_CAST27]], [[SUB_PTR_RHS_CAST28]]
+// CHECK11-NEXT: [[SUB_PTR_DIV30:%.*]] = sdiv exact i64 [[SUB_PTR_SUB29]], 4
+// CHECK11-NEXT: [[SUB31:%.*]] = sub nsw i64 [[SUB_PTR_DIV30]], 1
+// CHECK11-NEXT: [[ADD32:%.*]] = add nsw i64 [[SUB31]], 1
+// CHECK11-NEXT: [[DIV33:%.*]] = sdiv i64 [[ADD32]], 1
+// CHECK11-NEXT: [[MUL34:%.*]] = mul nsw i64 1, [[DIV33]]
+// CHECK11-NEXT: [[DIV35:%.*]] = sdiv i64 [[TMP30]], [[MUL34]]
+// CHECK11-NEXT: [[MUL36:%.*]] = mul nsw i64 [[DIV35]], 1
+// CHECK11-NEXT: [[ADD_PTR37:%.*]] = getelementptr inbounds i32, ptr [[TMP29]], i64 [[MUL36]]
+// CHECK11-NEXT: store ptr [[ADD_PTR37]], ptr [[__BEGIN123]], align 8
+// CHECK11-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST38:%.*]] = ptrtoint ptr [[TMP36]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST39:%.*]] = ptrtoint ptr [[TMP37]] to i64
+// CHECK11-NEXT: [[SUB_PTR_SUB40:%.*]] = sub i64 [[SUB_PTR_LHS_CAST38]], [[SUB_PTR_RHS_CAST39]]
+// CHECK11-NEXT: [[SUB_PTR_DIV41:%.*]] = sdiv exact i64 [[SUB_PTR_SUB40]], 4
+// CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i64 [[SUB_PTR_DIV41]], 1
+// CHECK11-NEXT: [[ADD43:%.*]] = add nsw i64 [[SUB42]], 1
+// CHECK11-NEXT: [[DIV44:%.*]] = sdiv i64 [[ADD43]], 1
+// CHECK11-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]]
+// CHECK11-NEXT: [[DIV46:%.*]] = sdiv i64 [[TMP35]], [[MUL45]]
+// CHECK11-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_10]], align 8
+// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
+// CHECK11-NEXT: [[SUB_PTR_LHS_CAST47:%.*]] = ptrtoint ptr [[TMP38]] to i64
+// CHECK11-NEXT: [[SUB_PTR_RHS_CAST48:%.*]] = ptrtoint ptr [[TMP39]] to i64
+// CHECK11-NEXT: [[SUB_PTR_SUB49:%.*]] = sub i64 [[SUB_PTR_LHS_CAST47]], [[SUB_PTR_RHS_CAST48]]
+// CHECK11-NEXT: [[SUB_PTR_DIV50:%.*]] = sdiv exact i64 [[SUB_PTR_SUB49]], 4
+// CHECK11-NEXT: [[SUB51:%.*]] = sub nsw i64 [[SUB_PTR_DIV50]], 1
+// CHECK11-NEXT: [[ADD52:%.*]] = add nsw i64 [[SUB51]], 1
+// CHECK11-NEXT: [[DIV53:%.*]] = sdiv i64 [[ADD52]], 1
+// CHECK11-NEXT: [[MUL54:%.*]] = mul nsw i64 1, [[DIV53]]
+// CHECK11-NEXT: [[MUL55:%.*]] = mul nsw i64 [[DIV46]], [[MUL54]]
+// CHECK11-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP34]], [[MUL55]]
+// CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i64 [[SUB56]], 1
+// CHECK11-NEXT: [[ADD_PTR58:%.*]] = getelementptr inbounds i32, ptr [[TMP33]], i64 [[MUL57]]
+// CHECK11-NEXT: store ptr [[ADD_PTR58]], ptr [[__BEGIN224]], align 8
+// CHECK11-NEXT: [[TMP40:%.*]] = load ptr, ptr [[__BEGIN123]], align 8
+// CHECK11-NEXT: store ptr [[TMP40]], ptr [[A]], align 8
+// CHECK11-NEXT: [[TMP41:%.*]] = load ptr, ptr [[__BEGIN224]], align 8
+// CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
+// CHECK11-NEXT: store i32 [[TMP42]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]]
+// CHECK11-NEXT: store i32 [[TMP43]], ptr [[TMP44]], align 4
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK11: omp.body.continue:
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK11: omp.inner.for.inc:
-// CHECK11-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
-// CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1
-// CHECK11-NEXT: store i64 [[ADD55]], ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK11-NEXT: [[ADD59:%.*]] = add nsw i64 [[TMP45]], 1
+// CHECK11-NEXT: store i64 [[ADD59]], ptr [[DOTOMP_IV]], align 8
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK11: omp.inner.for.end:
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK11: omp.loop.exit:
-// CHECK11-NEXT: [[TMP44:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK11-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
-// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP45]])
+// CHECK11-NEXT: [[TMP46:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
+// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP47]])
// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
// CHECK11: omp.precond.end:
// CHECK11-NEXT: ret void
More information about the cfe-commits
mailing list