[clang] [llvm] [AArch64][llvm] Remove +pcdphint gating (PR #181633)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 16 03:16:48 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
<details>
<summary>Changes</summary>
Remove gating of `stshh` since this is an instruction from the
HINT space, and therefore is a NOP on cores that don't implement
it, so gating is superfluous. gcc doesn't gate this, so remove
for better compatibility.
---
Full diff: https://github.com/llvm/llvm-project/pull/181633.diff
9 Files Affected:
- (modified) clang/test/Driver/aarch64-v96a.c (-4)
- (modified) clang/test/Driver/print-supported-extensions-aarch64.c (-1)
- (modified) llvm/lib/Target/AArch64/AArch64Features.td (-3)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+1-5)
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+2-4)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (-1)
- (modified) llvm/test/CodeGen/AArch64/arm64-prefetch-ir.ll (+2-2)
- (modified) llvm/test/MC/AArch64/armv9.6a-pcdphint.s (+5-13)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+1-3)
``````````diff
diff --git a/clang/test/Driver/aarch64-v96a.c b/clang/test/Driver/aarch64-v96a.c
index e0081bbbdabfe..6f43cfd8d36e5 100644
--- a/clang/test/Driver/aarch64-v96a.c
+++ b/clang/test/Driver/aarch64-v96a.c
@@ -62,10 +62,6 @@
// RUN: %clang -target aarch64 -march=armv9.6-a+occmo -### -c %s 2>&1 | FileCheck -check-prefix=V96A-OCCMO %s
// V96A-OCCMO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+occmo"
//
-// RUN: %clang -target aarch64 -march=armv9.6a+pcdphint -### -c %s 2>&1 | FileCheck -check-prefix=V96A-PCDPHINT %s
-// RUN: %clang -target aarch64 -march=armv9.6-a+pcdphint -### -c %s 2>&1 | FileCheck -check-prefix=V96A-PCDPHINT %s
-// V96A-PCDPHINT: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pcdphint"
-
// RUN: %clang -target aarch64 -march=armv9.6a+pops -### -c %s 2>&1 | FileCheck -check-prefix=V96A-POPS %s
// RUN: %clang -target aarch64 -march=armv9.6-a+pops -### -c %s 2>&1 | FileCheck -check-prefix=V96A-POPS %s
// V96A-POPS: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pops"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 1f8929e705e4c..7a6c628cd7238 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -58,7 +58,6 @@
// CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations
// CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
-// CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints
// CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: poe2 FEAT_S1POE2 Enable Stage 1 Permission Overlays Extension 2 instructions
// CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index ad6c4e6c102de..eafdd105339ae 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -564,9 +564,6 @@ def FeatureLSUI: ExtensionWithMArch<"lsui", "LSUI", "FEAT_LSUI",
def FeatureOCCMO: ExtensionWithMArch<"occmo", "OCCMO", "FEAT_OCCMO",
"Enable Armv9.6-A Outer cacheable cache maintenance operations">;
-def FeaturePCDPHINT: ExtensionWithMArch<"pcdphint", "PCDPHINT", "FEAT_PCDPHINT",
- "Enable Armv9.6-A Producer Consumer Data Placement hints">;
-
def FeaturePoPS: ExtensionWithMArch<"pops", "PoPS", "FEAT_PoPS",
"Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions">;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 8eb2d82da0ecb..9fb23d642f29f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -215,8 +215,6 @@ def HasSVEBFSCALE : Predicate<"Subtarget->isNonStreamingSVEorSME2Available()
AssemblerPredicateWithAll<(all_of FeatureSVEBFSCALE), "sve-bfscale">;
def HasSVE_F16F32MM : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_F16F32MM()">,
AssemblerPredicateWithAll<(all_of FeatureSVE_F16F32MM), "sve-f16f32mm">;
-def HasPCDPHINT : Predicate<"Subtarget->hasPCDPHINT()">,
- AssemblerPredicateWithAll<(all_of FeaturePCDPHINT), "pcdphint">;
def HasLSUI : Predicate<"Subtarget->hasLSUI()">,
AssemblerPredicateWithAll<(all_of FeatureLSUI), "lsui">;
def HasOCCMO : Predicate<"Subtarget->hasOCCMO()">,
@@ -1579,9 +1577,7 @@ def NOP : SystemNoOperands<0b000, "hint\t#0">;
def : InstAlias<"nop", (NOP)>;
-let Predicates = [HasPCDPHINT] in {
- def STSHH: STSHHI;
-}
+def STSHH: STSHHI;
// In order to be able to write readable assembly, LLVM should accept assembly
// inputs that use Branch Target Identification mnemonics, even with BTI disabled.
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index d91edf7a7b89d..d71aeb629bb3a 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2439,10 +2439,8 @@ def lookupPHintByName : SearchIndex {
let Key = ["Name"];
}
-let Requires = [{ {AArch64::FeaturePCDPHINT} }] in {
- def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
- def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
-}
+def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
+def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
// v9.6a Realm management extension enhancements
def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5ef3e2e50ec86..12e0e4dc7ddf8 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3934,7 +3934,6 @@ static const struct Extension {
{"sve-f16f32mm", {AArch64::FeatureSVE_F16F32MM}},
{"lsui", {AArch64::FeatureLSUI}},
{"occmo", {AArch64::FeatureOCCMO}},
- {"pcdphint", {AArch64::FeaturePCDPHINT}},
{"ssve-bitperm", {AArch64::FeatureSSVE_BitPerm}},
{"sme-mop4", {AArch64::FeatureSME_MOP4}},
{"sme-tmop", {AArch64::FeatureSME_TMOP}},
diff --git a/llvm/test/CodeGen/AArch64/arm64-prefetch-ir.ll b/llvm/test/CodeGen/AArch64/arm64-prefetch-ir.ll
index ca84de6616439..13756b88f05f8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-prefetch-ir.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-prefetch-ir.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=0 < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=1 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+v9a --global-isel=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+v9a --global-isel=1 < %s | FileCheck %s
define void @read_intent_prefetch(ptr %a, i64 %metadata) {
; CHECK-LABEL: read_intent_prefetch:
diff --git a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s
index b54409abe4a06..cfd7b098ab487 100644
--- a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s
+++ b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s
@@ -1,28 +1,20 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+pcdphint < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \
-// RUN: | llvm-objdump -d --mattr=+pcdphint --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \
-// RUN: | llvm-objdump -d --mattr=-pcdphint - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+pcdphint < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+pcdphint -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
stshh keep
// CHECK-INST: stshh keep
// CHECK-ENCODING: encoding: [0x1f,0x96,0x01,0xd5]
-// CHECK-ERROR: error: instruction requires: pcdphint
-// CHECK-UNKNOWN: d501961f msr S0_1_C9_C6_0, xzr
stshh strm
// CHECK-INST: stshh strm
// CHECK-ENCODING: encoding: [0x3f,0x96,0x01,0xd5]
-// CHECK-ERROR: error: instruction requires: pcdphint
-// CHECK-UNKNOWN: d501963f msr S0_1_C9_C6_1, xzr
prfm ir, [x0]
// CHECK-INST: prfm ir, [x0]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 7b3b196073aa7..327af9c53157e 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1448,7 +1448,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_F8F16MM, AArch64::AEK_LSFE,
AArch64::AEK_FPRCVT, AArch64::AEK_CMPBR,
AArch64::AEK_LSUI, AArch64::AEK_OCCMO,
- AArch64::AEK_PCDPHINT, AArch64::AEK_POPS,
AArch64::AEK_SVEAES, AArch64::AEK_SME_MOP4,
AArch64::AEK_SME_TMOP, AArch64::AEK_SVEBITPERM,
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
@@ -1461,6 +1460,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_F16F32MM, AArch64::AEK_MOPS_GO,
AArch64::AEK_POE2, AArch64::AEK_TEV,
AArch64::AEK_BTIE, AArch64::AEK_F64MM,
+ AArch64::AEK_POPS,
};
std::vector<StringRef> Features;
@@ -1567,7 +1567,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+cmpbr"));
EXPECT_TRUE(llvm::is_contained(Features, "+lsui"));
EXPECT_TRUE(llvm::is_contained(Features, "+occmo"));
- EXPECT_TRUE(llvm::is_contained(Features, "+pcdphint"));
EXPECT_TRUE(llvm::is_contained(Features, "+pops"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-mop4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-tmop"));
@@ -1748,7 +1747,6 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"cmpbr", "nocmpbr", "+cmpbr", "-cmpbr"},
{"lsui", "nolsui", "+lsui", "-lsui"},
{"occmo", "nooccmo", "+occmo", "-occmo"},
- {"pcdphint", "nopcdphint", "+pcdphint", "-pcdphint"},
{"pops", "nopops", "+pops", "-pops"},
{"sme-mop4", "nosme-mop4", "+sme-mop4", "-sme-mop4"},
{"sme-tmop", "nosme-tmop", "+sme-tmop", "-sme-tmop"},
``````````
</details>
https://github.com/llvm/llvm-project/pull/181633
More information about the cfe-commits
mailing list