[clang] Add riscv_simd.h for P extension intrinsics (PR #181115)

[Kito Cheng via cfe-commits]

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@@ -714,6 +714,13 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
       // Generic vector without riscv_vls_cc should fall through and pass by
       // reference.
       return coerceVLSVector(Ty, ABIVLen);
+    if (getContext().getTargetInfo().hasFeature("experimental-p") &&
+        VT->getVectorKind() == VectorKind::Generic &&
+        VT->getElementType()->isIntegerType() && (Size == 32 || Size == 64)) {
+      uint64_t EltSize = getContext().getTypeSize(VT->getElementType());
+      if (EltSize == 8 || EltSize == 16 || EltSize == 32)
+        return ABIArgInfo::getDirect();
+    }
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kito-cheng wrote:

We do not need these changes. In fact, adding this logic causes ABI incompatibility. Modules compiled with p-ext and without p-ext now have different function signatures.

We have declare "Fixed-length vectors are treated as aggregates." in the [psABI](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#integer-calling-convention), also it already did right thing without those change.

Although I can understand why you want to make this change — because the LLVM IR lowered by clang uses i32 (RV32) / i64 (RV64) to pass values, and there are casts between i32/i64 and fixed-length vectors — in practice these extra instructions only look ugly at the LLVM IR level and do not affect code generation quality and correctness. 

https://github.com/llvm/llvm-project/pull/181115